Abstract: Aspects of the embodiments are directed to systems, methods, and devices for generating a design of experiments (DOE) matrix, the DOE matrix comprising a set of possible combinations of values for a plurality of electrical parameters; iteratively applying each combination of values for the plurality of electrical parameters to one or more memory pins; determining a margin response for each combination of values; generating a prediction function based on a correlation of the margin response and each combination of values; and optimizing the plurality of electrical parameters based on the prediction function.

Abstract: Aspects of the embodiments are directed to systems, methods, and devices for generating a design of experiments (DOE) matrix, the DOE matrix comprising a set of possible combinations of values for a plurality of electrical parameters; iteratively applying each combination of values for the plurality of electrical parameters to one or more memory pins; determining a margin response for each combination of values; generating a prediction function based on a correlation of the margin response and each combination of values; and optimizing the plurality of electrical parameters based on the prediction function.

Abstract: According to some embodiments, a method and apparatus are provided to determine a worst-case setup and hold bit pattern stream associated with a load on a bus, and determine a time shift to apply to an incoming bit pattern being conveyed relative to a DLL associated with the load.

Abstract: According to some embodiments, a method and apparatus are provided to determine a worst-case setup and hold bit pattern stream associated with a load on a bus, and determine a time shift to apply to an incoming bit pattern being conveyed relative to a DLL associated with the load.

Abstract: Embodiments are generally directed to systems, methods, and apparatuses for suppressing power supply noise using data scrambling in double data rate memory systems. In some embodiments, an integrated circuit includes a transmit data path to transmit data to one or more memory devices. The transmit data path may include scrambling logic to generate, in parallel, N pseudo random outputs that are uncorrelated with each other. The output data and the pseudo random outputs are input to XOR logic. The transmit data path transmits the output the of XOR logic which has a substantially white frequency spectrum. Other embodiments are described and claimed.

Abstract: Embodiments are generally directed to systems, methods, and apparatuses for suppressing power supply noise using data scrambling in double data rate memory systems. In some embodiments, an integrated circuit includes a transmit data path to transmit data to one or more memory devices. The transmit data path may include scrambling logic to generate, in parallel, N pseudo random outputs that are uncorrelated with each other. The output data and the pseudo random outputs are input to XOR logic. The transmit data path transmits the output the of XOR logic which has a substantially white frequency spectrum. Other embodiments are described and claimed.

Abstract: A method of reducing electromagnetic interference and improving signal quality in printed circuit boards with plane splits is described. The use of a lossy slot filling is described. The lossy filling is applied above plane splits and squeezed into the slots. The lossy material helps to damp antenna resonance.

Abstract: A method of reducing electromagnetic interference and improving signal quality in printed circuit boards with plane splits is described. The use of a lossy slot filling is described. The lossy filling is applied above plane splits and squeezed into the slots. The lossy material helps to damp antenna resonance.