Patents by Inventor Adam J. Norman

Adam J. Norman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10262751
    Abstract: Aspects of the embodiments are directed to systems, methods, and devices for generating a design of experiments (DOE) matrix, the DOE matrix comprising a set of possible combinations of values for a plurality of electrical parameters; iteratively applying each combination of values for the plurality of electrical parameters to one or more memory pins; determining a margin response for each combination of values; generating a prediction function based on a correlation of the margin response and each combination of values; and optimizing the plurality of electrical parameters based on the prediction function.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: April 16, 2019
    Assignee: Intel Corporation
    Inventors: Oseghale O. Uduebho, Adam J. Norman
  • Publication number: 20180088849
    Abstract: Aspects of the embodiments are directed to systems, methods, and devices for generating a design of experiments (DOE) matrix, the DOE matrix comprising a set of possible combinations of values for a plurality of electrical parameters; iteratively applying each combination of values for the plurality of electrical parameters to one or more memory pins; determining a margin response for each combination of values; generating a prediction function based on a correlation of the margin response and each combination of values; and optimizing the plurality of electrical parameters based on the prediction function.
    Type: Application
    Filed: September 29, 2016
    Publication date: March 29, 2018
    Applicant: Intel Corporation
    Inventors: Oseghale O. Uduebho, Adam J. Norman
  • Patent number: 9104635
    Abstract: According to some embodiments, a method and apparatus are provided to determine a worst-case setup and hold bit pattern stream associated with a load on a bus, and determine a time shift to apply to an incoming bit pattern being conveyed relative to a DLL associated with the load.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: August 11, 2015
    Assignee: Intel Corporation
    Inventors: Oseghale O. Uduebho, Adam J. Norman
  • Publication number: 20140059318
    Abstract: According to some embodiments, a method and apparatus are provided to determine a worst-case setup and hold bit pattern stream associated with a load on a bus, and determine a time shift to apply to an incoming bit pattern being conveyed relative to a DLL associated with the load.
    Type: Application
    Filed: December 28, 2011
    Publication date: February 27, 2014
    Inventors: Oseghale O. Uduebho, Adam J. Norman
  • Patent number: 8503678
    Abstract: Embodiments are generally directed to systems, methods, and apparatuses for suppressing power supply noise using data scrambling in double data rate memory systems. In some embodiments, an integrated circuit includes a transmit data path to transmit data to one or more memory devices. The transmit data path may include scrambling logic to generate, in parallel, N pseudo random outputs that are uncorrelated with each other. The output data and the pseudo random outputs are input to XOR logic. The transmit data path transmits the output the of XOR logic which has a substantially white frequency spectrum. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: August 6, 2013
    Assignee: Intel Corporation
    Inventors: Maynard C. Falconer, Christopher P. Mozak, Adam J. Norman
  • Publication number: 20100153699
    Abstract: Embodiments are generally directed to systems, methods, and apparatuses for suppressing power supply noise using data scrambling in double data rate memory systems. In some embodiments, an integrated circuit includes a transmit data path to transmit data to one or more memory devices. The transmit data path may include scrambling logic to generate, in parallel, N pseudo random outputs that are uncorrelated with each other. The output data and the pseudo random outputs are input to XOR logic. The transmit data path transmits the output the of XOR logic which has a substantially white frequency spectrum. Other embodiments are described and claimed.
    Type: Application
    Filed: December 23, 2009
    Publication date: June 17, 2010
    Inventors: MAYNARD C. FALCONER, Christopher P. Mozak, Adam J. Norman
  • Patent number: 6706974
    Abstract: A method of reducing electromagnetic interference and improving signal quality in printed circuit boards with plane splits is described. The use of a lossy slot filling is described. The lossy filling is applied above plane splits and squeezed into the slots. The lossy material helps to damp antenna resonance.
    Type: Grant
    Filed: January 18, 2002
    Date of Patent: March 16, 2004
    Assignee: Intel Corporation
    Inventors: Juan Chen, Adam J. Norman, Ponniah Ilavarasan
  • Publication number: 20030136580
    Abstract: A method of reducing electromagnetic interference and improving signal quality in printed circuit boards with plane splits is described. The use of a lossy slot filling is described. The lossy filling is applied above plane splits and squeezed into the slots. The lossy material helps to damp antenna resonance.
    Type: Application
    Filed: January 18, 2002
    Publication date: July 24, 2003
    Inventors: Juan Chen, Adam J. Norman, Ponniah Ilavarasan