Patents by Inventor Adam J. Whitworth
Adam J. Whitworth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8327523Abstract: There is provided a method of making two electrically separated inductors using deposition and wet-etching techniques, which inductors are formed by interwinding one of the inductors within the other inductor on the same planar level. In still another aspect of the invention, there is provided a method of making various levels inductors, each level having at least two electrically separated inductors, using deposition and wet-etching techniques. The inductors on each planar level are formed by interwinding one of the inductors within the other inductor, and then stacking these in a preferred manner. In still another aspect, there is provided a manner of connecting together inductors formed according to the above methods in order to achieve various inductor configurations.Type: GrantFiled: November 28, 2006Date of Patent: December 11, 2012Assignee: Semiconductor Components Industries, LLCInventors: Adam J. Whitworth, Wenjiang Zeng
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Publication number: 20080258263Abstract: A method of fabricating a N+/P+ zener diode where the reverse breakdown occurs in a controlled, and uniform manner leading to improved speed of operation and increase in current handling capability.Type: ApplicationFiled: April 20, 2007Publication date: October 23, 2008Inventors: Harry Yue Gee, Adam J. Whitworth, Umesh Sharma
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Publication number: 20080120828Abstract: There is provided a method of making two electrically separated inductors using deposition and wet-etching techniques, which inductors are formed by interwinding one of the inductors within the other inductor on the same planar level. In still another aspect of the invention, there is provided a method of making various levels inductors, each level having at least two electrically separated inductors, using deposition and wet-etching techniques. The inductors on each planar level are formed by interwinding one of the inductors within the other inductor, and then stacking these in a preferred manner. In still another aspect, there is provided a manner of connecting together inductors formed according to the above methods in order to achieve various inductor configurations.Type: ApplicationFiled: November 28, 2006Publication date: May 29, 2008Inventors: Adam J. Whitworth, Wenjiang Zeng
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Patent number: 7321241Abstract: The present invention is directed to bidirectional buffer with slew rate control in at least one direction. The present invention is also directed to a method of bidirectionally transmitting signals with slew rate control in at least one direction.Type: GrantFiled: June 15, 2006Date of Patent: January 22, 2008Assignee: California Micro DevicesInventors: Chadwick N. Marak, Jeffrey C. Dunnihoo, Adam J. Whitworth
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Publication number: 20070290711Abstract: The present invention is directed to bidirectional buffer with slew rate control in at least one direction. The present invention is also directed to a method of bidirectionally transmitting signals with slew rate control in at least one direction.Type: ApplicationFiled: June 15, 2006Publication date: December 20, 2007Inventors: Chadwick N. Marak, Jeffrey C. Dunnihoo, Adam J. Whitworth
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Patent number: 6747476Abstract: An active termination circuit for clamping a signal on a transmission line in an electronic device is described. The active termination circuit is configured to clamp the signal on the transmission line to one of a first reference voltage level and a second reference voltage level. In one embodiment, the active termination circuit includes a bottom clamping transistor coupled to a first potential having a bottom clamping transistor control node arranged for clamping the signal at about a first reference voltage. The active termination circuit also includes a top clamping transistor coupled to a second potential having a top clamping transistor control node arranged for clamping the signal at about a second reference voltage as well as an inverter unit coupling the transmission line to stabilizing capacitors for stabilizing control node voltages.Type: GrantFiled: March 13, 2003Date of Patent: June 8, 2004Assignee: California Micro DevicesInventor: Adam J. Whitworth
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Publication number: 20030214319Abstract: An active termination circuit for clamping a signal on a transmission line in an electronic device is described. The active termination circuit is configured to clamp the signal on the transmission line to one of a first reference voltage level and a second reference voltage level. In one embodiment, the active termination circuit includes a bottom clamping transistor coupled to a first potential having a bottom clamping transistor control node arranged for clamping the signal at about a first reference voltage. The active termination circuit also includes a top clamping transistor coupled to a second potential having a top clamping transistor control node arranged for clamping the signal at about a second reference voltage as well as an inverter unit coupling the transmission line to stabilizing capacitors for stabilizing control node voltages.Type: ApplicationFiled: March 13, 2003Publication date: November 20, 2003Inventor: Adam J. Whitworth
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Patent number: 6556040Abstract: An active termination circuit for clamping a signal on a transmission line in an electronic device is described. The active termination circuit is configured to clamp the signal on the transmission line to one of a first reference voltage level and a second reference voltage level. In one embodiment, the active termination circuit includes a bottom clamping transistor coupled to a first potential having a bottom clamping transistor control node arranged for clamping the signal at about a first reference voltage. The active termination circuit also includes a top clamping transistor coupled to a second potential having a top clamping transistor control node arranged for clamping the signal at about a second reference voltage as well as an inverter unit coupling the transmission line to stabilizing capacitors for stabilizing control node voltages.Type: GrantFiled: July 31, 2002Date of Patent: April 29, 2003Assignee: California Micro DevicesInventor: Adam J. Whitworth
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Patent number: 6512393Abstract: An active termination circuit for clamping a signal on a transmission line in an electronic device is described. The active termination circuit is configured to clamp the signal on the transmission line to one of a first reference voltage level and a second reference voltage level. The active termination circuit includes a bottom clamping transistor having a bottom clamping transistor first node coupled to a transmission line at a transmission line node, a bottom clamping transistor second node coupled to a first potential, and a bottom clamping transistor control node coupled to a first bias voltage supply. The circuit also includes a top clamping transistor having a top clamping transistor first node coupled to the transmission line at the transmission line node, a top clamping transistor second node coupled to a second potential, and a top clamping transistor control node coupled to a second bias voltage supply.Type: GrantFiled: November 15, 2000Date of Patent: January 28, 2003Assignee: California Micro Devices, Inc.Inventors: Adam J. Whitworth, Anthony Russell
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Publication number: 20020190747Abstract: An active termination circuit for clamping a signal on a transmission line in an electronic device is described. The active termination circuit is configured to clamp the signal on the transmission line to one of a first reference voltage level and a second reference voltage level. In one embodiment, the active termination circuit includes a bottom clamping transistor coupled to a first potential having a bottom clamping transistor control node arranged for clamping the signal at about a first reference voltage. The active termination circuit also includes a top clamping transistor coupled to a second potential having a top clamping transistor control node arranged for clamping the signal at about a second reference voltage as well as an inverter unit coupling the transmission line to stabilizing capacitors for stabilizing control node voltages.Type: ApplicationFiled: July 31, 2002Publication date: December 19, 2002Applicant: California Micro DevicesInventor: Adam J. Whitworth
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Patent number: 6329837Abstract: An active termination circuit for clamping signals on a bus in an electronic device is described. The active termination circuit is configured to clamp the signals on the bus to one of a first reference voltage level and a second reference voltage level. In one embodiment, the active termination circuit includes bottom clamping transistors coupled to a first potential having bottom clamping transistor control nodes arranged for clamping the signal at about a first reference voltage. The active termination circuit also includes top clamping transistors coupled to a second potential having top clamping transistor control nodes arranged for clamping the signal at about a second reference voltage.Type: GrantFiled: November 2, 2000Date of Patent: December 11, 2001Assignee: California Micro Devices CorporationInventors: Adam J. Whitworth, Dominick Richiuso
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Patent number: 6326805Abstract: An active termination circuit for clamping a signal on a transmission line in an electronic device is described. The active termination circuit is configured to clamp the signal on the transmission line to one of a first reference voltage level and a second reference voltage level. In one embodiment, the active termination circuit includes a bottom clamping transistor coupled to a first potential having a bottom clamping transistor control node arranged for clamping the signal at about a first reference voltage. The active termination circuit also includes a top clamping transistor coupled to a second potential having a top clamping transistor control node arranged for clamping the signal at about a second reference voltage.Type: GrantFiled: November 2, 2000Date of Patent: December 4, 2001Assignee: California Micro Devices CorporationInventors: Adam J. Whitworth, Dominick Richiuso
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Patent number: 6326804Abstract: An active termination circuit having localized potential supplies for clamping a signal on a transmission line in an electronic device is described. The active termination circuit is configured to clamp the signal on the transmission line to one of a first reference voltage level and a second reference voltage level. In one embodiment, the active termination circuit includes a bottom clamping transistor coupled to a first localized potential having a bottom clamping transistor control node arranged for clamping the signal at about a first reference voltage. The active termination circuit also includes a top clamping transistor coupled to a second localized potential having a top clamping transistor control node arranged for clamping the signal at about a second reference voltage.Type: GrantFiled: November 2, 2000Date of Patent: December 4, 2001Assignee: California Micro DevicesInventors: Adam J. Whitworth, Dominick Richiuso
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Patent number: 6323676Abstract: An active termination circuit for protecting a node against an ESD voltage spike is described. The ESD protection circuit includes a bottom ESD protection transistor having a first node coupled to a first potential and a bottom ESD protection transistor intrinsic diode reverse biasedly coupling said node to a first reference voltage supply and a bottom threshold reference transistor coupled to the first reference voltage supply. The bottom threshold reference transistor provides a first bias voltage to the bottom ESD protection transistor gate that biases the bottom clamping transistor gate at about a first threshold voltage from the first reference voltage representing a threshold voltage of said bottom ESD protection transistor.Type: GrantFiled: November 2, 2000Date of Patent: November 27, 2001Assignee: California Micro Devices CorporationInventors: Adam J. Whitworth, Dominick Richiuso
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Patent number: 6323675Abstract: An active termination circuit for clamping a signal on a transmission line in an electronic device in a tri-state mode is described. The active circuit includes a tri-state output buffer and a bottom clamping transistor coupled to GND and the tri-state output buffer having a bottom clamping transistor control node arranged for clamping the signal at about GND. A bottom threshold reference transistor coupled to a first reference voltage supply configured to supply a first reference voltage. The bottom threshold reference transistor provides a first bias voltage to the bottom clamping transistor control node that biases the bottom clamping transistor control node at about a first threshold voltage above GND where the first threshold voltage represents a threshold voltage of the bottom clamping transistor.Type: GrantFiled: November 2, 2000Date of Patent: November 27, 2001Assignee: California Micro Devices CorporationInventors: Adam J. Whitworth, Dominick Richiuso