Patents by Inventor Adam J. Williams
Adam J. Williams has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923561Abstract: A pouch cell includes an electrode assembly and a body forming a gas headspace within the pouch. Tabs of the electrode assembly may extend through or around the body and out of the pouch. Gas from the electrode assembly may collect in the gas headspace. The body may accommodate a vent mechanism that also extends out of the pouch.Type: GrantFiled: March 30, 2022Date of Patent: March 5, 2024Assignee: ZAF Energy Systems, IncorporatedInventors: Randy Moore, Shiloh J. Williams, Adam Weisenstein
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Patent number: 10714605Abstract: A transistor includes a substrate, a channel layer coupled to the substrate, a source electrode coupled to the channel layer, a drain electrode coupled to the channel layer, and a gate electrode coupled to the channel layer between the source electrode and the drain electrode. The gate electrode has a length dimension of less than 50 nanometers near the channel layer, and the channel layer includes at least a first GaN layer and a first graded AlGaN layer on the first GaN layer.Type: GrantFiled: December 12, 2018Date of Patent: July 14, 2020Assignee: HRL Laboratories, LLCInventors: Jeong-Sun Moon, Andrea Corrion, Joel C. Wong, Adam J. Williams
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Publication number: 20190252535Abstract: A transistor includes a substrate, a channel layer coupled to the substrate, a source electrode coupled to the channel layer, a drain electrode coupled to the channel layer, and a gate electrode coupled to the channel layer between the source electrode and the drain electrode. The gate electrode has a length dimension of less than 50 nanometers near the channel layer, and the channel layer includes at least a first GaN layer and a first graded AlGaN layer on the first GaN layer.Type: ApplicationFiled: December 12, 2018Publication date: August 15, 2019Applicant: HRL Laboratories, LLCInventors: Jeong-Sun MOON, Andrea CORRION, Joel C. WONG, Adam J. WILLIAMS
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Patent number: 10134851Abstract: A diode includes: a semiconductor substrate; a cathode metal layer contacting a bottom of the substrate; a semiconductor drift layer on the substrate; a graded aluminum gallium nitride (AlGaN) semiconductor barrier layer on the drift layer and having a larger bandgap than the drift layer, the barrier layer having a top surface and a bottom surface between the drift layer and the top surface, the barrier layer having an increasing aluminum composition from the bottom surface to the top surface; and an anode metal layer directly contacting the top surface of the barrier layer.Type: GrantFiled: December 14, 2017Date of Patent: November 20, 2018Assignee: HRL Laboratories, LLCInventors: Rongming Chu, Yu Cao, Zijian “Ray” Li, Adam J. Williams
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Publication number: 20180114837Abstract: A diode includes: a semiconductor substrate; a cathode metal layer contacting a bottom of the substrate; a semiconductor drift layer on the substrate; a graded aluminum gallium nitride (AlGaN) semiconductor barrier layer on the drift layer and having a larger bandgap than the drift layer, the barrier layer having a top surface and a bottom surface between the drift layer and the top surface, the barrier layer having an increasing aluminum composition from the bottom surface to the top surface; and an anode metal layer directly contacting the top surface of the barrier layer.Type: ApplicationFiled: December 14, 2017Publication date: April 26, 2018Inventors: Rongming Chu, Yu Cao, Zijian "Ray" Li, Adam J. Williams
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Patent number: 9899482Abstract: A diode includes: a semiconductor substrate; a cathode metal layer contacting a bottom of the substrate; a semiconductor drift layer on the substrate; a graded aluminum gallium nitride (AlGaN) semiconductor barrier layer on the drift layer and having a larger bandgap than the drift layer, the barrier layer having a top surface and a bottom surface between the drift layer and the top surface, the barrier layer having an increasing aluminum composition from the bottom surface to the top surface; and an anode metal layer directly contacting the top surface of the barrier layer.Type: GrantFiled: April 7, 2016Date of Patent: February 20, 2018Assignee: HRL Laboratories, LLCInventors: Rongming Chu, Yu Cao, Zijian Li, Adam J. Williams
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Publication number: 20170047453Abstract: A diode includes: a semiconductor substrate; a cathode metal layer contacting a bottom of the substrate; a semiconductor drift layer on the substrate; a graded aluminum gallium nitride (AlGaN) semiconductor barrier layer on the drift layer and having a larger bandgap than the drift layer, the barrier layer having a top surface and a bottom surface between the drift layer and the top surface, the barrier layer having an increasing aluminum composition from the bottom surface to the top surface; and an anode metal layer directly contacting the top surface of the barrier layer.Type: ApplicationFiled: April 7, 2016Publication date: February 16, 2017Inventors: Rongming Chu, Yu Cao, Zijian "Ray" Li, Adam J. Williams
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Patent number: 9419122Abstract: A method of making a stepped field gate for an FET including forming a first set of layers having a passivation layer on a barrier layer of the FET and a first etch stop layer over the first passivation layer, forming additional sets of layers having alternating passivation layer and etch stop layers, successively removing portions of each set of layers using lithography and reactive ion etching to form stepped passivation layers and a gate foot, applying a mask having an opening defining an extent of a stepped field-plate gate, and forming the stepped field plate gate and the gate foot by plating through the opening in the mask.Type: GrantFiled: September 29, 2015Date of Patent: August 16, 2016Assignee: HRL Laboratories, LLCInventors: Andrea Corrion, Keisuke Shinohara, Miroslav Micovic, Rongming Chu, David F. Brown, Adam J. Williams, Dean C. Regan, Joel C. Wong
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Patent number: 9202880Abstract: A method of making a stepped field gate for an FET including forming a first set of layers having a passivation layer on a barrier layer of the FET and a first etch stop layer over the first passivation layer, forming additional sets of layers having alternating passivation layer and etch stop layers, successively removing portions of each set of layers using lithography and reactive ion etching to form stepped passivation layers and a gate foot, applying a mask having an opening defining an extent of a stepped field-plate gate, and forming the stepped field plate gate and the gate foot by plating through the opening in the mask.Type: GrantFiled: August 30, 2013Date of Patent: December 1, 2015Assignee: HRL Laboratories, LLCInventors: Andrea Corrion, Keisuke Shinohara, Miroslav Micovic, Rongming Chu, David F. Brown, Adam J. Williams, Dean C. Regan, Joel C. Wong
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Patent number: 9059200Abstract: A field effect transistor (FET) includes a III-Nitride channel layer, a III-Nitride barrier layer on the channel layer, wherein the barrier layer has an energy bandgap greater than the channel layer, a source electrode electrically coupled to one of the III-Nitride layers, a drain electrode electrically coupled to one of the III-Nitride layers, a gate insulator layer stack for electrically insulating a gate electrode from the barrier layer and the channel layer, the gate insulator layer stack including an insulator layer, such as SiN, and an AlN layer, the gate electrode in a region between the source electrode and the drain electrode and in contact with the insulator layer, and wherein the AlN layer is in contact with one of the III-Nitride layers.Type: GrantFiled: August 26, 2014Date of Patent: June 16, 2015Assignee: HRL Laboratories, LLCInventors: Rongming Chu, David F. Brown, Xu Chen, Adam J. Williams, Karim S. Boutros
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Patent number: 8941118Abstract: A III-nitride transistor includes a III-nitride channel layer, a barrier layer over the channel layer, the barrier layer having a thickness of 1 to 10 nanometers, a dielectric layer on top of the barrier layer, a source electrode contacting the channel layer, a drain electrode contacting the channel layer, a gate trench extending through the dielectric layer and barrier layer and having a bottom located within the channel layer, a gate insulator lining the gate trench and extending over the dielectric layer, and a gate electrode in the gate trench and extending partially toward the source and the drain electrodes to form an integrated gate field-plate, wherein a distance between an interface of the channel layer and the barrier layer and the bottom of the gate trench is greater than 0 nm and less than or equal to 5 nm.Type: GrantFiled: September 30, 2013Date of Patent: January 27, 2015Assignee: HRL Laboratories, LLCInventors: Rongming Chu, David F. Brown, Adam J. Williams
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Patent number: 8853709Abstract: A field effect transistor (FET) includes a III-Nitride channel layer, a III-Nitride barrier layer on the channel layer, wherein the barrier layer has an energy bandgap greater than the channel layer, a source electrode electrically coupled to one of the III-Nitride layers, a drain electrode electrically coupled to one of the III-Nitride layers, a gate insulator layer stack for electrically insulating a gate electrode from the barrier layer and the channel layer, the gate insulator layer stack including an insulator layer, such as SiN, and an AlN layer, the gate electrode in a region between the source electrode and the drain electrode and in contact with the insulator layer, and wherein the AlN layer is in contact with one of the III-Nitride layers.Type: GrantFiled: April 25, 2012Date of Patent: October 7, 2014Assignee: HRL Laboratories, LLCInventors: Rongming Chu, David F. Brown, Xu Chen, Adam J. Williams, Karim S. Boutros
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Publication number: 20130026495Abstract: A field effect transistor (FET) includes a III-Nitride channel layer, a III-Nitride barrier layer on the channel layer, wherein the barrier layer has an energy bandgap greater than the channel layer, a source electrode electrically coupled to one of the III-Nitride layers, a drain electrode electrically coupled to one of the III-Nitride layers, a gate insulator layer stack for electrically insulating a gate electrode from the barrier layer and the channel layer, the gate insulator layer stack including an insulator layer, such as SiN, and an AlN layer, the gate electrode in a region between the source electrode and the drain electrode and in contact with the insulator layer, and wherein the AlN layer is in contact with one of the III-Nitride layers.Type: ApplicationFiled: April 25, 2012Publication date: January 31, 2013Applicant: HRL LOBORATORIES, LLCInventors: Rongming Chu, David F. Brown, Xu Chen, Adam J. Williams, Karim S. Boutros