Patents by Inventor Adam Jerome White

Adam Jerome White has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200350220
    Abstract: A chip includes a metal layer, a portion of a first sawbow line, and a portion of a second sawbow line. The portion of the first sawbow line and the portion of the second sawbow line respectively correspond to the first sawbow line and the second sawbow line in a cut state. The portions of the first and second sawbow lines may be on different layers, and the metal layer may be arranged over the portion of the first sawbow line and/or the portion of the second sawbow line to hide at least one of the portions of the sawbow lines in the cut state.
    Type: Application
    Filed: April 30, 2019
    Publication date: November 5, 2020
    Inventors: Harold Garth HANSON, Siamak DELSHADPOUR, Adam Jerome WHITE, Steven DANIEL
  • Patent number: 10318416
    Abstract: A method for implementing a non-volatile counter using non-volatile memory is disclosed. In an embodiment, the method involves distributing operations for storing a low word of a counter in non-volatile memory across memory cells in a memory array in the non-volatile memory, and storing additional bits of the counter in the non-volatile memory in memory cells outside of the memory array, wherein the location in the memory array at which the low word is stored is determined for each count based on the upper bits of the counter.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: June 11, 2019
    Assignee: NXP B.V.
    Inventor: Adam Jerome White
  • Publication number: 20180336130
    Abstract: A method for implementing a non-volatile counter using non-volatile memory is disclosed. In an embodiment, the method involves distributing operations for storing a low word of a counter in non-volatile memory across memory cells in a memory array in the non-volatile memory, and storing additional bits of the counter in the non-volatile memory in memory cells outside of the memory array, wherein the location in the memory array at which the low word is stored is determined for each count based on the upper bits of the counter.
    Type: Application
    Filed: May 18, 2017
    Publication date: November 22, 2018
    Applicant: NXP B.V.
    Inventor: Adam Jerome White
  • Patent number: 10050618
    Abstract: A signal management circuit includes a first input terminal to receive a first signal. A first logic portion is coupled to the first input terminal and configured to provide a first output signal. A second logic portion is coupled to receive a second signal and configured to provide a second output signal. The second signal is based on the first output signal and the first signal. An output terminal is coupled to provide a third output signal based on the first output signal and the second output signal.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: August 14, 2018
    Assignee: NXP USA, INC.
    Inventor: Adam Jerome White