Abstract: In an integrated circuit (IC) analysis, a reference IC layout is stored. Instructions are readable and executable by an electronic processor to perform an IC analysis method, including: receiving layer images of a physical IC; extracting polygons depicted in the layer images; detecting errors in the physical IC by applying homeomorphic error detection to compare the extracted polygons with polygons of the reference IC layout; and displaying the detected errors on the display. The detecting of errors may include detecting an error comprising a topological inequivalence between an extracted polygon or pair of polygons and a polygon or pair of polygons of the reference IC layout. The detecting of errors may include detecting an error comprising a topological coverage error.

Abstract: The present disclosure provides a method for generating a spatially resolved netlist that includes generating a netlist based on integrated circuit (IC) layout data and standard cell library data, the netlist including cell and net definitions associated with the IC; determining position data for respective cells and nets based on the IC layout data; mapping the position data to respective cell and net definitions in the netlist; and generating a spatially resolved netlist that includes the mapped position data to respective cell and net definitions.

Abstract: In an integrated circuit (IC) analysis, a reference IC layout is stored. Instructions are readable and executable by an electronic processor to perform an IC analysis method, including: receiving layer images of a physical IC; extracting polygons depicted in the layer images; detecting errors in the physical IC by applying homeomorphic error detection to compare the extracted polygons with polygons of the reference IC layout; and displaying the detected errors on the display. The detecting of errors may include detecting an error comprising a topological inequivalence between an extracted polygon or pair of polygons and a polygon or pair of polygons of the reference IC layout. The detecting of errors may include detecting an error comprising a topological coverage error.

Abstract: In an integrated circuit (IC) assessment method, an artificial intelligence (AI) component comprising at least one artificial neural network (ANN) is trained to transform layout rendering tiles of a rendering of a reference IC into corresponding reference layout image tiles extracted from at least one layout image of the reference IC. Using the trained AI component, standard cell layout renderings of a library of GDSII or OASIS standard cell layout renderings are transformed into as-fabricated standard cell layout renderings forming a library of as fabricated standard cell layout renderings. Instantiated standard cells and their placements in the layout image of an IC-under-test are identified by matching the instantiated standard cells with corresponding as-fabricated standard cell layout renderings retrieved from the library of as fabricated standard cell layout renderings.

Abstract: In an integrated circuit (IC) assessment method, an artificial intelligence (AI) component comprising at least one artificial neural network (ANN) is trained to transform layout rendering tiles of a rendering of a reference IC into corresponding reference layout image tiles extracted from at least one layout image of the reference IC. Using the trained AI component, standard cell layout renderings of a library of GDSII or OASIS standard cell layout renderings are transformed into as-fabricated standard cell layout renderings forming a library of as fabricated standard cell layout renderings. Instantiated standard cells and their placements in the layout image of an IC-under-test are identified by matching the instantiated standard cells with corresponding as-fabricated standard cell layout renderings retrieved from the library of as fabricated standard cell layout renderings.

Abstract: In an integrated circuit (IC) assessment method, an artificial intelligence (AI) component comprising at least one artificial neural network (ANN) is trained to transform layout rendering tiles of a rendering of a reference IC into corresponding reference layout image tiles extracted from at least one layout image of the reference IC. Using the trained AI component, standard cell layout renderings of a library of GDSII or OASIS standard cell layout renderings are transformed into as-fabricated standard cell layout renderings forming a library of as fabricated standard cell layout renderings. Instantiated standard cells and their placements in the layout image of an IC-under-test are identified by matching the instantiated standard cells with corresponding as-fabricated standard cell layout renderings retrieved from the library of as fabricated standard cell layout renderings.

Abstract: In an integrated circuit (IC) analysis, a reference IC layout is stored. Instructions are readable and executable by an electronic processor to perform an IC analysis method, including: receiving layer images of a physical IC; extracting polygons depicted in the layer images; detecting errors in the physical IC by applying homeomorphic error detection to compare the extracted polygons with polygons of the reference IC layout; and displaying the detected errors on the display. The detecting of errors may include detecting an error comprising a topological inequivalence between an extracted polygon or pair of polygons and a polygon or pair of polygons of the reference IC layout. The detecting of errors may include detecting an error comprising a topological coverage error.

Abstract: In an integrated circuit (IC) assessment method, an artificial intelligence (AI) component comprising at least one artificial neural network (ANN) is trained to transform layout rendering tiles of a rendering of a reference IC into corresponding reference layout image tiles extracted from at least one layout image of the reference IC. Using the trained AI component, standard cell layout renderings of a library of GDSII or OASIS standard cell layout renderings are transformed into as-fabricated standard cell layout renderings forming a library of as fabricated standard cell layout renderings. Instantiated standard cells and their placements in the layout image of an IC-under-test are identified by matching the instantiated standard cells with corresponding as-fabricated standard cell layout renderings retrieved from the library of as fabricated standard cell layout renderings.

Abstract: The present disclosure provides a method for generating a spatially resolved netlist that includes generating a netlist based on integrated circuit (IC) layout data and standard cell library data, the netlist including cell and net definitions associated with the IC; determining position data for respective cells and nets based on the IC layout data; mapping the position data to respective cell and net definitions in the netlist; and generating a spatially resolved netlist that includes the mapped position data to respective cell and net definitions.

Abstract: The present disclosure provides a circuit design validation system. In one embodiment, the system includes polygon extraction circuitry to determine, based on layer images of a fabricated integrated circuit (IC), a plurality of polygons associated with a layer of the fabricated IC; and cell pattern matching circuitry to search the polygons defined within a layer image of the fabricated IC to determine a match between a cell template of a standard cell library and the plurality of polygons defined within the layer image of the fabricated IC.

Abstract: In an integrated circuit (IC) assessment method, an artificial intelligence (AI) component comprising at least one artificial neural network (ANN) is trained to transform layout rendering tiles of a rendering of a reference IC into corresponding reference layout image tiles extracted from at least one layout image of the reference IC. Using the trained AI component, standard cell layout renderings of a library of GDSII or OASIS standard cell layout renderings are transformed into as-fabricated standard cell layout renderings forming a library of as fabricated standard cell layout renderings. Instantiated standard cells and their placements in the layout image of an IC-under-test are identified by matching the instantiated standard cells with corresponding as-fabricated standard cell layout renderings retrieved from the library of as fabricated standard cell layout renderings.