Abstract: A system for remote control of lights and small appliances utilizing miniature remote control units, and a method for easily and simply setting which remote controls control which item(s). Unlike conventional remote controls which are moved from place to place, these miniature remote controls are so small they may be removably mounted at each location needed, unobtrusively or even hidden. Receivers for the remote signal are described manufactured within a lamp socket assembly, a very short light bulb socket adapter, the light bulb itself, a wallswitch dimmer and an outlet adapter. One remote control can control multiple receivers, or vice versa, or any other combination, without conflict and with the combination set up or changed more intuitively than in completing systems. Appliances may be turned on or off and lights may be dimmed precisely or set flashing in unison to summon help.

Abstract: A shortened adapter for a light bulb socket with highly overlapped male and female parts with an insulating hand-ring that extends only partially over the external surface of the adapter's female threading so it fits into the unthreaded collar of a light bulb socket, thereby significantly reducing the light bulb displacement. The shortened adapter can respond to an incoming signal and control the output of a light bulb. A reversible ring on the insulating hand-ring can change the adapter from being a dimmer to being an on-off control. A mechanism is disclosed to reversibly lock the adapter onto a light bulb. A miniature remote controller to work with the adapter is provided that has many advantages because of its very small size and compact shape. Further, one such controller can control several lights and several such controllers can control a single light in arbitrary combinations selected by the user.

Abstract: A system for remote control of lights and small appliances utilizing miniature remote control units, and a method for easily and simply setting which remote controls control which item(s). Unlike conventional remote controls which are moved from place to place, these miniature remote controls are so small they may be removably mounted at each location needed, unobtrusively or even hidden. Receivers for the remote signal are described manufactured within a lamp socket assembly, a very short light bulb socket adapter, the light bulb itself, a wallswitch dimmer and an outlet adapter. One remote control can control multiple receivers, or vice versa, or any other combination, without conflict and with the combination set up or changed more intuitively than in completing systems. Appliances may be turned on or off and lights may be dimmed precisely or set flashing in unison to summon help.

Abstract: A shortened adapter for a light bulb socket with highly overlapped male and female parts with an insulating hand-ring that extends only partially over the external surface of the adapter's female threading so it fits into the unthreaded collar of a light bulb socket, thereby significantly reducing the light bulb displacement. The shortened adapter can respond to an incoming signal and control the output of a light bulb. A reversible ring on the insulating hand-ring can change the adapter from being a dimmer to being an on-off control. A mechanism is disclosed to reversibly lock the adapter onto a light bulb. A miniature remote controller to work with the adapter is provided that has many advantages because of its very small size and compact shape. Further, one such controller can control several lights and several such controllers can control a single light in arbitrary combinations selected by the user.

Abstract: A system and method for generating a clock signal having spread spectrum modulation. The method involves generating a clock signal by generating edge positions for edges of the clock signal from a digital representation of a timing for each edge to impart spread spectrum modulation to the clock signal. A programmable modulator is provided that generates digital values representing edge positions for edges of a clock signal based on at least one of a time-varying period value and a time-varying duty-cycle value. The programmable modulator may comprise a first circuit, called a period modulation circuit, that generates a time-varying digital period value, and a second circuit, called a duty-cycle modulation circuit, that generates a time-varying digital duty-cycle value. The time-varying period values and time-varying duty cycle values are processed to produce a digital edge position value that specifies an edge position for a clock signal.

Abstract: A system and method for generating a clock signal having spread spectrum modulation. The method involves generating a clock signal by generating edge positions for edges of the clock signal from a digital representation of a timing for each edge to impart spread spectrum modulation to the clock signal. A programmable modulator is provided that generates digital values representing edge positions for edges of a clock signal based on at least one of a time-varying period value and a time-varying duty-cycle value. The programmable modulator may comprise a first circuit, called a period modulation circuit, that generates a time-varying digital period value, and a second circuit, called a duty-cycle modulation circuit, that generates a time-varying digital duty-cycle value. The time-varying period values and time-varying duty cycle values are processed to produce a digital edge position value that specifies an edge position for a clock signal.

Abstract: The waveform generator includes a free-running ring oscillator, and algebra module, a switching module and an output module. The free-running ring oscillator includes a plurality of delay elements connected in a loop and a plurality of taps disposed between the delay elements, with each tap providing a uniquely phased, oscillating transition signal. The algebra module generates an output signal indicating a first rising edge of the arbitrary waveform in response to an input signal. The switching module includes a switch input port in electrical communication with the algebra data output port, a plurality of switch tap input ports in electrical communication with the free-running ring oscillator taps and switch output port. At the switch output port, the switch module provides a first transition signal selected from one of the plurality of free running ring oscillator taps in response to the signal indicative of a first rising edge received at the switch input port.

Abstract: A system and method for generating a clock signal having spread spectrum modulation. The method involves generating a clock signal by generating edge positions for edges of the clock signal from a digital representation of a timing for each edge to impart spread spectrum modulation to the clock signal. A programmable modulator is provided that generates digital values representing edge positions for edges of a clock signal based on at least one of a time-varying period value and a time-varying duty-cycle value. The programmable modulator may comprise a first circuit, called a period modulation circuit, that generates a time-varying digital period value, and a second circuit, called a duty-cycle modulation circuit, that generates a time-varying digital duty-cycle value. The time-varying period values and time-varying duty cycle values are processed to produce a digital edge position value that specifies an edge position for a clock signal.

Abstract: A digitally programmable delay circuit comprising a plurality of transistors connected in parallel with each other and to a line carrying a signal having an edge to be delayed. One or more of the transistors are selected by a delay control signal to impose a delay amount to the edge, wherein the delay control signal is based on a desired delay amount and a measure of instantaneous process, voltage and temperature conditions of an integrated circuit in which the plurality of transistors are implemented. A selector circuit is responsive to the delay control signal and converts the delay control signal into one or more transistor selection signals to activate one or more of the plurality of transistors. The plurality of transistors may comprise a first sub-circuit having a plurality of transistors of a first type (e.g., P-type) connected in parallel with each other in a ladder configuration, and a second sub-circuit comprising a plurality of transistors of a second type (e.g.

Abstract: A clock signal generation system and method to distribute at least one clock signal to a plurality of points on a circuit board using a plurality of digitally programmable delay circuits each of which delays the clock signal by a desired amount so as to synchronize arrival of the clock signal when distributed to each of the plurality of points on the circuit. Each digitally programmable delay circuit comprises a plurality of circuit stages connected in series with each other. Each circuit stage comprises a plurality of transistors of a first type (e.g., P-type) connected in parallel with each other, and a plurality of transistors of a second type (e.g., N-type) connected in parallel with each other. In each circuit stage, one or more of the plurality of transistors of the first type are selected to delay a rising edge, and one or more of the plurality of transistors of a second type are selected to delay a falling edge.

Abstract: A high speed serializer-deserializer (SerDes) that passes significantly more data through a channel for a given analog bandwidth and signal-to-noise ratio. This SerDes technique involves converting a plurality of bits to be transferred to positions of edges of a waveform that is transmitted over at least one transmission wire from a source to a destination. The plurality of bits are converted to edges in order to position edges such that more than k inter-edge spacings are possible over a range of spacings between T and kT, where k is a real number greater than 1 and T is the minimum spacing between consecutive edges. An edge position translation scheme that maps patterns in a stream of input bits to a corresponding spacing between a rising edge and a falling edge of the waveform, or between a falling edge and a rising edge of the waveform.

Abstract: A digitally programmable delay circuit comprising a plurality of transistors connected in parallel with each other and to a line carrying a signal having an edge to be delayed. One or more of the transistors are selected by a delay control signal to impose a delay amount to the edge, wherein the delay control signal is based on a desired delay amount and a measure of instantaneous process, voltage and temperature conditions of an integrated circuit in which the plurality of transistors are implemented. A selector circuit is responsive to the delay control signal and converts the delay control signal into one or more transistor selection signals to activate one or more of the plurality of transistors. The plurality of transistors may comprise a first sub-circuit having a plurality of transistors of a first type (e.g., P-type) connected in parallel with each other in a ladder configuration, and a second sub-circuit comprising a plurality of transistors of a second type (e.g.

Abstract: A waveform generator includes a plurality of delay elements such as in a delay line circuit of a free-running oscillator, phase locked loop (PLL) circuit or delay locked loop (DLL) circuit, an algebra module, a switching module and an output module. The oscillator includes a plurality of delay elements and a plurality of taps disposed between the delay elements, with each tap providing a uniquely phased, oscillating transition signal. The algebra module includes an algebra data input port, a clock input port and an algebra data output port. The algebra module generates a signal at the algebra data output port indicating a first rising edge of the arbitrary waveform in response to a signal received at the algebra data input port. The switching module includes a switch input port in electrical communication with the algebra data output port, a plurality of switch tap input ports in electrical communication oscillator taps and switch output port.

Abstract: The present invention relates to a method of adaptively enhancing a digital image based on image content. An accurate determination of image type permits implementation of an image enhancement technique that is matched to the image type. The method is advantageous when the image type of the received images can vary. In one embodiment the method distinguishes between line art images and continuous tone images. The method includes application of a window to a pixels in a source array. The number of colors in each of the resulting windowed arrays is determined. Each color can optionally be defined as a range of colors. A color range total is calculated from the sum of the number of windowed arrays in one or more subsets of the plurality of possible numbers of colors. Image type is determined in response to the color range total and an enhancement process matched to the image type is applied to the digital image data.

Abstract: A clock signal distributor circuit for maintaining a phase relationship between one or more remote operating nodes and a reference clock on a chip, wherein there is a clock signal drive path and a clock signal sense path in a distribution limb for each remote node. The clock signal distributor circuit comprises a variable signal delay circuit in the clock signal drive path, a variable signal delay circuit in the clock signal sense path, and a feedback circuit that causes at least one variable signal delay circuit to change its signal delay based on the sense path.

Abstract: The waveform generator includes a free-running ring oscillator, an algebra module, a switching module and an output module. The free-running ring oscillator includes a plurality of delay elements connected in a loop and a plurality of taps disposed between the delay elements, with each tap providing a uniquely phased, oscillating transition signal. The algebra module generates an output signal indicating a first rising edge of the arbitrary waveform in response to an input signal. The switching module includes a switch input port in electrical communication with the algebra data output port, a plurality of switch tap input ports in electrical communication with the free-running ring oscillator taps and switch output port. At the switch output port, the switch module provides a first transition signal selected from one of the plurality of free-running ring oscillator taps in response to the signal indicative of a first rising edge received at the switch input port.

Abstract: A pixel image enhancement system which operates on color or monochrome source images to produce output cells the same size as the source pixels but not spatially coincident or one-to-one correspondent with them. By operating upon a set of input pixels surrounding each output cell with a set of logic operations implementing unique Boolean equations, the system generates “case numbers” characterizing inferred-edge pieces within each output cell. A rendering subsystem, responsive to the case numbers and source-pixel colors, then produces signals for driving an output device (printer or display) to display the output cells, including the inferred-edge pieces, to the best of the output device's ability and at its resolution.

Abstract: The waveform generator includes a free-running ring oscillator, an algebra module, a switching module and an output module. The free-running ring oscillator includes a plurality of delay elements connected in a loop and a plurality of taps disposed between the delay elements, with each tap providing a uniquely phased, oscillating transition signal. The algebra module generates an output signal indicating a first rising edge of the arbitrary waveform in response to an input signal. The switching module includes a switch input port in electrical communication with the algebra data output port, a plurality of switch tap input ports in electrical communication with the free-running ring oscillator taps and switch output port. At the switch output port, the switch module provides a first transition signal selected from one of the plurality of free-running ring oscillator taps in response to the signal indicative of a first rising edge received at the switch input port.

Abstract: The waveform generator includes a free-running ring oscillator, an algebra module, a switching module and an output module. The free-running ring oscillator includes a plurality of delay elements connected in a loop and a plurality of taps disposed between the delay elements, with each tap providing a uniquely phased, oscillating transition signal. The algebra module generates an output signal indicating a first rising edge of the arbitrary waveform in response to an input signal. The switching module includes a switch input port in electrical communication with the algebra data output port, a plurality of switch tap input ports in electrical communication with the free-running ring oscillator taps and switch output port. At the switch output port, the switch module provides a first transition signal selected from one of the plurality of free-running ring oscillator taps in response to the signal indicative of a first rising edge received at the switch input port.

Abstract: A waveform generator includes a plurality of delay elements such as in a delay line circuit of a free-running oscillator, phase locked loop (PLL) circuit or delay locked loop (DLL) circuit, an algebra module, a switching module and an output module. The oscillator includes a plurality of delay elements and a plurality of taps disposed between the delay elements, with each tap providing a uniquely phased, oscillating transition signal. The algebra module includes an algebra data input port, a clock input port and an algebra data output port. The algebra module generates a signal at the algebra data output port indicating a first rising edge of the arbitrary waveform in response to a signal received at the algebra data input port. The switching module includes a switch input port in electrical communication with the algebra data output port, a plurality of switch tap input ports in electrical communication oscillator taps and switch output port.