Patents by Inventor Adam L. Olson

Adam L. Olson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11563027
    Abstract: Microelectronic devices include a lower deck and an upper deck, each comprising a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A lower array of pillars extends through the stack structure of the lower deck, and an upper array of pillars extends through the stack structure of the upper deck. Along an interface between the lower deck and the upper deck, the pillars of the lower array align with the pillars of the upper array. At least at elevations comprising bases of the pillars, a pillar density of the pillars of the lower array differs from a pillar density of the pillars of the upper array, “pillar density” being a number of pillars per unit of horizontal area of the respective array. Related methods and electronic systems are also disclosed.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: January 24, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Md Zakir Ullah, Xiaosong Zhang, Adam L. Olson, Mohammad Moydul Islam, Tien Minh Quan Tran, Chao Zhu, Zhigang Yang, Merri L. Carlson, Hui Chin Chong, David A. Kewley, Kok Siak Tang
  • Patent number: 11532477
    Abstract: A self-assembled nanostructure comprises first domains and second domains. The first domains comprise a first block of a block copolymer material and an activatable catalyst. The second domains comprise a second block and substantially without the activatable catalyst. The activatable catalyst is capable of generating catalyst upon application of activation energy, and the generated catalyst is capable of reacting with a metal oxide precursor to provide a metal oxide. A semiconductor structure comprises such self-assembled nanostructure on a substrate.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: December 20, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Nicholas Hendricks, Adam L. Olson, William R. Brown, Ho Seop Eom, Xue Chen, Kaveri Jain, Scott Schuldenfrei
  • Publication number: 20220189827
    Abstract: A microelectronic device comprises a microelectronic device structure having a memory array region and a staircase region. The microelectronic device structure comprises a stack structure having tiers each comprising a conductive structure and an insulative structure; staircase structures confined within the staircase region and having steps comprising edges of the tiers of the stack structure within the deck and the additional deck; and semiconductive pillar structures confined within the memory array region and extending through the stack structures. The stack structure comprises a deck comprising a group of the tiers; an additional deck overlying the deck and comprising an additional group of the tiers; and an interdeck section between the deck and the additional deck and comprising a dielectric structure confined within the memory array region, and another group of the tiers within vertical boundaries of the dielectric structure and confined within the staircase region.
    Type: Application
    Filed: February 24, 2022
    Publication date: June 16, 2022
    Inventors: Bo Zhao, Nancy M. Lomeli, Lifang Xu, Adam L. Olson
  • Patent number: 11282747
    Abstract: A microelectronic device comprises a microelectronic device structure having a memory array region and a staircase region. The microelectronic device structure comprises a stack structure having tiers each comprising a conductive structure and an insulative structure; staircase structures confined within the staircase region and having steps comprising edges of the tiers of the stack structure within the deck and the additional deck; and semiconductive pillar structures confined within the memory array region and extending through the stack structures. The stack structure comprises a deck comprising a group of the tiers; an additional deck overlying the deck and comprising an additional group of the tiers; and an interdeck section between the deck and the additional deck and comprising a dielectric structure confined within the memory array region, and another group of the tiers within vertical boundaries of the dielectric structure and confined within the staircase region.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: March 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Bo Zhao, Nancy M. Lomeli, Lifang Xu, Adam L. Olson
  • Publication number: 20220077177
    Abstract: Microelectronic devices include a lower deck and an upper deck, each comprising a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A lower array of pillars extends through the stack structure of the lower deck, and an upper array of pillars extends through the stack structure of the upper deck. Along an interface between the lower deck and the upper deck, the pillars of the lower array align with the pillars of the upper array. At least at elevations comprising bases of the pillars, a pillar density of the pillars of the lower array differs from a pillar density of the pillars of the upper array, “pillar density” being a number of pillars per unit of horizontal area of the respective array. Related methods and electronic systems are also disclosed.
    Type: Application
    Filed: September 9, 2020
    Publication date: March 10, 2022
    Inventors: Md Zakir Ullah, Xiaosong Zhang, Adam L. Olson, Mohammad Moydul Islam, Tien Minh Quan Tran, Chao Zhu, Zhigang Yang, Merri L. Carlson, Hui Chin Chong, David A. Kewley, Kok Siak Tang
  • Publication number: 20210407930
    Abstract: A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.
    Type: Application
    Filed: September 14, 2021
    Publication date: December 30, 2021
    Inventors: Rohit Kothari, Adam L. Olson, John D. Hopkins, Jeslin J. Wu
  • Patent number: 11189526
    Abstract: Methods of forming staircase structures. The method comprises forming a patterned hardmask over tiers. An exposed portion of an uppermost tier is removed to form an uppermost stair. A first liner material is formed over the patterned hardmask and the uppermost tier, and a portion of the first liner material is removed to form a first liner and expose an underlying tier. An exposed portion of the underlying tier is removed to form an underlying stair in the underlying tier. A second liner material is formed over the patterned hardmask, the first liner, and the second liner. A portion of the second liner material is removed to form a second liner and expose another underlying tier. An exposed portion of the another underlying tier is removed to form another underlying stair. The patterned hardmask is removed. Staircase structures and semiconductor device structure are also disclosed.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: November 30, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Lance Williamson, Adam L. Olson, Kaveri Jain, Robert Dembi, William R. Brown
  • Patent number: 11127691
    Abstract: A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: September 21, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Rohit Kothari, Adam L. Olson, John D. Hopkins, Jeslin J. Wu
  • Publication number: 20210265216
    Abstract: A microelectronic device comprises a microelectronic device structure having a memory array region and a staircase region. The microelectronic device structure comprises a stack structure having tiers each comprising a conductive structure and an insulative structure; staircase structures confined within the staircase region and having steps comprising edges of the tiers of the stack structure within the deck and the additional deck; and semiconductive pillar structures confined within the memory array region and extending through the stack structures. The stack structure comprises a deck comprising a group of the tiers; an additional deck overlying the deck and comprising an additional group of the tiers; and an interdeck section between the deck and the additional deck and comprising a dielectric structure confined within the memory array region, and another group of the tiers within vertical boundaries of the dielectric structure and confined within of the staircase region.
    Type: Application
    Filed: February 24, 2020
    Publication date: August 26, 2021
    Inventors: Bo Zhao, Nancy M. Lomeli, Lifang Xu, Adam L. Olson
  • Publication number: 20210167079
    Abstract: Methods of improving adhesion between a photoresist and conductive or insulating structures. The method comprises forming a slot through at least a portion of alternating conductive structures and insulating structures on a substrate. Portions of the conductive structures or of the insulating structures are removed to form recesses in the conductive structures or in the insulating structures. A photoresist is formed over the alternating conductive structures and insulating structures and within the slot. Methods of improving adhesion between a photoresist and a spin-on dielectric material are also disclosed, as well as methods of forming a staircase structure.
    Type: Application
    Filed: February 11, 2021
    Publication date: June 3, 2021
    Inventors: Rohit Kothari, Jason C. McFarland, Jason Reece, David A. Kewley, Adam L. Olson
  • Patent number: 10930659
    Abstract: Methods of improving adhesion between a photoresist and conductive or insulating structures. The method comprises forming a slot through at least a portion of alternating conductive structures and insulating structures on a substrate. Portions of the conductive structures or of the insulating structures are removed to form recesses in the conductive structures or in the insulating structures. A photoresist is formed over the alternating conductive structures and insulating structures and within the slot. Methods of improving adhesion between a photoresist and a spin-on dielectric material are also disclosed, as well as methods of forming a staircase structure.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: February 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Rohit Kothari, Jason C. McFarland, Jason Reece, David A. Kewley, Adam L. Olson
  • Publication number: 20200211981
    Abstract: A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: Rohit Kothari, Adam L. Olson, John D. Hopkins, Jeslin J. Wu
  • Publication number: 20200194305
    Abstract: Methods of forming staircase structures. The method comprises forming a patterned hardmask over tiers. An exposed portion of an uppermost tier is removed to form an uppermost stair. A first liner material is formed over the patterned hardmask and the uppermost tier, and a portion of the first liner material is removed to form a first liner and expose an underlying tier. An exposed portion of the underlying tier is removed to form an underlying stair in the underlying tier. A second liner material is formed over the patterned hardmask, the first liner, and the second liner. A portion of the second liner material is removed to form a second liner and expose another underlying tier. An exposed portion of the another underlying tier is removed to form another underlying stair. The patterned hardmask is removed. Staircase structures and semiconductor device structure are also disclosed.
    Type: Application
    Filed: February 24, 2020
    Publication date: June 18, 2020
    Inventors: Lance Williamson, Adam L. Olson, Kaveri Jain, Robert Dembi, William R. Brown
  • Patent number: 10672657
    Abstract: A method of forming a semiconductor device assembly comprises forming tiers comprising conductive structures and insulating structures in a stacked arrangement over a substrate. Portions of the tiers are selectively removed to form a stair step structure comprising a selected number of steps exhibiting different widths corresponding to variances in projected error associated with forming the steps. Contact structures are formed on the steps of the stair step structure. Semiconductor device structures and semiconductor devices are also described.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: June 2, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Matthew Park, Adam L. Olson, Jixin Yu
  • Patent number: 10600681
    Abstract: Methods of forming staircase structures. The method comprises forming a patterned hardmask over tiers. An exposed portion of an uppermost tier is removed to form an uppermost stair. A first liner material is formed over the patterned hardmask and the uppermost tier, and a portion of the first liner material is removed to form a first liner and expose an underlying tier. An exposed portion of the underlying tier is removed to form an underlying stair in the underlying tier. A second liner material is formed over the patterned hardmask, the first liner, and the second liner. A portion of the second liner material is removed to form a second liner and expose another underlying tier. An exposed portion of the another underlying tier is removed to form another underlying stair. The patterned hardmask is removed. Staircase structures and semiconductor device structure are also disclosed.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: March 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Lance Williamson, Adam L. Olson, Kaveri Jain, Robert Dembi, William R. Brown
  • Patent number: 10600796
    Abstract: Methods of improving adhesion between a photoresist and conductive or insulating structures. The method comprises forming a slot through at least a portion of alternating conductive structures and insulating structures on a substrate. Portions of the conductive structures or of the insulating structures are removed to form recesses in the conductive structures or in the insulating structures. A photoresist is formed over the alternating conductive structures and insulating structures and within the slot. Methods of improving adhesion between a photoresist and a spin-on dielectric material are also disclosed, as well as methods of forming a staircase structure.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: March 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Rohit Kothari, Jason C. McFarland, Jason Reece, David A. Kewley, Adam L. Olson
  • Patent number: 10522461
    Abstract: A method of forming a semiconductor structure comprises forming pools of acidic or basic material in a substrate structure. A resist is formed over the pools of acidic or basic material and the substrate structure. The acidic or basic material is diffused from the pools into portions of the resist proximal to the pools more than into portions of the resist distal to the pools. Then, the resist is exposed to a developer to remove a greater amount of the resist portions proximal to the pools compared to the resist portions distal to the pools to form openings in the resist. The openings have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure. The method may further comprise forming features in the openings of the resist. The features have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: December 31, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Adam L. Olson, Kaveri Jain, Lijing Gou, William R. Brown, Ho Seop Eom, Xue (Gloria) Chen, Anton J. deVilliers
  • Publication number: 20190355735
    Abstract: Methods of improving adhesion between a photoresist and conductive or insulating structures. The method comprises forming a slot through at least a portion of alternating conductive structures and insulating structures on a substrate. Portions of the conductive structures or of the insulating structures are removed to form recesses in the conductive structures or in the insulating structures. A photoresist is formed over the alternating conductive structures and insulating structures and within the slot. Methods of improving adhesion between a photoresist and a spin-on dielectric material are also disclosed, as well as methods of forming a staircase structure.
    Type: Application
    Filed: August 5, 2019
    Publication date: November 21, 2019
    Inventors: Rohit Kothari, Jason C. McFarland, Jason Reece, David A. Kewley, Adam L. Olson
  • Patent number: 10453748
    Abstract: A method of forming a semiconductor device assembly comprises forming tiers comprising conductive structures and insulating structures in a stacked arrangement over a substrate. Portions of the tiers are selectively removed to form a stair step structure comprising a selected number of steps exhibiting different widths corresponding to variances in projected error associated with forming the steps. Contact structures are formed on the steps of the stair step structure. Semiconductor device structures and semiconductor devices are also described.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: October 22, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Matthew Park, Adam L. Olson, Jixin Yu
  • Publication number: 20190206726
    Abstract: Methods of forming staircase structures. The method comprises forming a patterned hardmask over tiers. An exposed portion of an uppermost tier is removed to form an uppermost stair. A first liner material is formed over the patterned hardmask and the uppermost tier, and a portion of the first liner material is removed to form a first liner and expose an underlying tier. An exposed portion of the underlying tier is removed to form an underlying stair in the underlying tier. A second liner material is formed over the patterned hardmask, the first liner, and the second liner. A portion of the second liner material is removed to form a second liner and expose another underlying tier. An exposed portion of the another underlying tier is removed to form another underlying stair. The patterned hardmask is removed. Staircase structures and semiconductor device structure are also disclosed.
    Type: Application
    Filed: October 18, 2018
    Publication date: July 4, 2019
    Inventors: Lance Williamson, Adam L. Olson, Kaveri Jain, Robert Dembi, William R. Brown