Patents by Inventor Adam Lake
Adam Lake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230360307Abstract: One embodiment provides a graphics processor comprising a block of execution resources, a cache memory, a cache memory prefetcher, and circuitry including a programmable neural network unit, the programmable neural network unit comprising a network hardware block including circuitry to perform neural network operations and activation operations for a layer of a neural network, the programmable neural network unit addressable by cores within the block of graphics cores and the neural network hardware block configured to perform operations associated with a neural network configured to determine a prefetch pattern for the cache memory prefetcher.Type: ApplicationFiled: May 1, 2023Publication date: November 9, 2023Applicant: Intel CorporationInventors: HUGUES LABBE, DARREL PALKE, SHERINE ABDELHAK, JILL BOYCE, VARGHESE GEORGE, SCOTT JANUS, ADAM LAKE, ZHIJUN LEI, ZHENGMIN LI, MIKE MACPHERSON, CARL MARSHALL, SELVAKUMAR PANNEER, PRASOONKUMAR SURTI, KARTHIK VEERAMANI, DEEPAK VEMBAR, VALLABHAJOSYULA SRINIVASA SOMAYAZULU
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Patent number: 11676322Abstract: One embodiment provides for a graphics processor comprising a block of graphics compute units, a graphics processor pipeline coupled to the block of graphics compute units, and a programmable neural network unit including one or more neural network hardware blocks. The programmable neural network unit is coupled with the block of graphics compute units and the graphics processor pipeline. The one or more neural network hardware blocks include hardware to perform neural network operations and activation operations for a layer of a neural network. The programmable neural network unit can configure settings of one or more hardware blocks within the graphics processor pipeline based on a machine learning model trained to optimize performance of a set of workloads.Type: GrantFiled: October 13, 2021Date of Patent: June 13, 2023Assignee: Intel CorporationInventors: Hugues Labbe, Darrel Palke, Sherine Abdelhak, Jill Boyce, Varghese George, Scott Janus, Adam Lake, Zhijun Lei, Zhengmin Li, Mike Macpherson, Carl Marshall, Selvakumar Panneer, Prasoonkumar Surti, Karthik Veeramani, Deepak Vembar, Vallabhajosyula Srinivasa Somayazulu
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Patent number: 11557085Abstract: Embodiments are directed to neural network processing for multi-object three-dimensional (3D) modeling. An embodiment of a computer-readable storage medium includes executable computer program instructions for obtaining data from multiple cameras, the data including multiple images, and generating a 3D model for 3D imaging based at least in part on the data from the cameras, wherein generating the 3D model includes one or more of performing processing with a first neural network to determine temporal direction based at least in part on motion of one or more objects identified in an image of the multiple images or performing processing with a second neural network to determine semantic content information for an image of the multiple images.Type: GrantFiled: December 4, 2020Date of Patent: January 17, 2023Assignee: Intel CorporationInventors: Jill Boyce, Soethiha Soe, Selvakumar Panneer, Adam Lake, Nilesh Jain, Deepak Vembar, Glen J. Anderson, Varghese George, Carl Marshall, Scott Janus, Saurabh Tangri, Karthik Veeramani, Prasoonkumar Surti
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Publication number: 20220058853Abstract: One embodiment provides for a graphics processor comprising a block of graphics compute units, a graphics processor pipeline coupled to the block of graphics compute units, and a programmable neural network unit including one or more neural network hardware blocks. The programmable neural network unit is coupled with the block of graphics compute units and the graphics processor pipeline. The one or more neural network hardware blocks include hardware to perform neural network operations and activation operations for a layer of a neural network. The programmable neural network unit can configure settings of one or more hardware blocks within the graphics processor pipeline based on a machine learning model trained to optimize performance of a set of workloads.Type: ApplicationFiled: October 13, 2021Publication date: February 24, 2022Applicant: Intel CorporationInventors: HUGUES LABBE, DARREL PALKE, SHERINE ABDELHAK, JILL BOYCE, VARGHESE GEORGE, SCOTT JANUS, ADAM LAKE, ZHIJUN LEI, ZHENGMIN LI, MIKE MACPHERSON, CARL MARSHALL, SELVAKUMAR PANNEER, PRASOONKUMAR SURTI, KARTHIK VEERAMANI, DEEPAK VEMBAR, VALLABHAJOSYULA SRINIVASA SOMAYAZULU
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Publication number: 20220051476Abstract: Apparatus and method for efficient graphics processing including ray tracing. For example, one embodiment of a graphics processor comprises: execution hardware logic to execute graphics commands and render images; an interface to couple functional units of the execution hardware logic to a tiled resource; and a tiled resource manager to manage access by the functional units to the tiled resource, a functional unit of the execution hardware logic to generate a request with a hash identifier (ID) to request access to a portion of the tiled resource, wherein the tiled resource manager is to determine whether a portion of the tiled resource identified by the hash ID exists, and if not, to allocate a new portion of the tiled resource and associate the new portion with the hash ID.Type: ApplicationFiled: December 23, 2020Publication date: February 17, 2022Inventors: Sven Woop, Michael J. Doyle, Sreenivas Kothandaraman, Karthik Vaidyanathan, Abhishek R. Appu, Carsten Benthin, Prasoonkumar Surti, Holger GRUEN, Stephen Junkins, Adam Lake, Bret G. Alfieri, Gabor Liktor, Joshua Barczak, Won-Jong Lee
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Publication number: 20220051467Abstract: Apparatus and method for efficient graphics processing including ray tracing. For example, one embodiment of a graphics processor comprises: execution hardware logic to execute graphics commands and render images; an interface to couple functional units of the execution hardware logic to a tiled resource; and a tiled resource manager to manage access by the functional units to the tiled resource, a functional unit of the execution hardware logic to generate a request with a hash identifier (ID) to request access to a portion of the tiled resource, wherein the tiled resource manager is to determine whether a portion of the tiled resource identified by the hash ID exists, and if not, to allocate a new portion of the tiled resource and associate the new portion with the hash ID.Type: ApplicationFiled: December 23, 2020Publication date: February 17, 2022Inventors: Sven Woop, Michael J. Doyle, Sreenivas Kothandaraman, Karthik Vaidyanathan, Abhishek R. Appu, Carsten Benthin, Prasoonkumar Surti, Holger GRUEN, Stephen Junkins, Adam Lake, Bret G. Alfieri, Gabor Liktor, Joshua Barczak, Won-Jong Lee
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Patent number: 11151769Abstract: One embodiment provides for a graphics processor comprising a block of graphics compute units, a graphics processor pipeline coupled to the block of graphics compute units, and a programmable neural network unit including one or more neural network hardware blocks. The programmable neural network unit is coupled with the block of graphics compute units and the graphics processor pipeline. The one or more neural network hardware blocks include hardware to perform neural network operations and activation operations for a layer of a neural network. The programmable neural network unit can configure settings of one or more hardware blocks within the graphics processor pipeline based on a machine learning model trained to optimize performance of a set of workloads.Type: GrantFiled: August 9, 2019Date of Patent: October 19, 2021Assignee: Intel CorporationInventors: Hugues Labbe, Darrel Palke, Sherine Abdelhak, Jill Boyce, Varghese George, Scott Janus, Adam Lake, Zhijun Lei, Zhengmin Li, Mike Macpherson, Carl Marshall, Selvakumar Panneer, Prasoonkumar Surti, Karthik Veeramani, Deepak Vembar, Vallabhajosyula Srinivasa Somayazulu
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Patent number: 11120620Abstract: An apparatus to facilitate variable rate shading is disclosed. The apparatus comprises one or more processors to generate a course pixel output value for a pixel block, generate a gradient value comprising a gradient of the course pixel output value using neighbor pixel data and process the pixels in the pixel block using the gradient value to generate a fine pixel value for one or more pixels.Type: GrantFiled: June 24, 2020Date of Patent: September 14, 2021Assignee: Intel CorporationInventors: Filip Strugar, Trapper McFerron, Adam Lake
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Publication number: 20210090327Abstract: Embodiments are directed to neural network processing for multi-object three-dimensional (3D) modeling. An embodiment of a computer-readable storage medium includes executable computer program instructions for obtaining data from multiple cameras, the data including multiple images, and generating a 3D model for 3D imaging based at least in part on the data from the cameras, wherein generating the 3D model includes one or more of performing processing with a first neural network to determine temporal direction based at least in part on motion of one or more objects identified in an image of the multiple images or performing processing with a second neural network to determine semantic content information for an image of the multiple images.Type: ApplicationFiled: December 4, 2020Publication date: March 25, 2021Applicant: Intel CorporationInventors: Jill Boyce, Soethiha Soe, Selvakamur Panneer, Adam Lake, Nilesh Jain, Deepak Vembar, Glen J. Anderson, Varghese George, Carl Marshall, Scott Janus, Saurabh Tangri, Karthik Veeramani, Prasoonkumar Surti
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Publication number: 20210012563Abstract: An apparatus to facilitate variable rate shading is disclosed. The apparatus comprises one or more processors to generate a course pixel output value for a pixel block, generate a gradient value comprising a gradient of the course pixel output value using neighbor pixel data and process the pixels in the pixel block using the gradient value to generate a fine pixel value for one or more pixels.Type: ApplicationFiled: June 24, 2020Publication date: January 14, 2021Applicant: Intel CorporationInventors: Filip Strugar, Trapper McFerron, Adam Lake
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Patent number: 10861225Abstract: Embodiments are directed to neural network processing for multi-object three-dimensional (3D) modeling. An embodiment of a computer-readable storage medium includes executable computer program instructions for obtaining data from multiple cameras, the data including multiple images, and generating a 3D model for 3D imaging based at least in part on the data from the cameras, wherein generating the 3D model includes one or more of performing processing with a first neural network to determine temporal direction based at least in part on motion of one or more objects identified in an image of the multiple images or performing processing with a second neural network to determine semantic content information for an image of the multiple images.Type: GrantFiled: December 27, 2018Date of Patent: December 8, 2020Assignee: INTEL CORPORATIONInventors: Jill Boyce, Soethiha Soe, Selvakumar Panneer, Adam Lake, Nilesh Jain, Deepak Vembar, Glen J. Anderson, Varghese George, Carl Marshall, Scott Janus, Saurabh Tangri, Karthik Veeramani, Prasoonkumar Surti
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Publication number: 20200051309Abstract: One embodiment provides for a graphics processor comprising a block of graphics compute units, a graphics processor pipeline coupled to the block of graphics compute units, and a programmable neural network unit including one or more neural network hardware blocks. The programmable neural network unit is coupled with the block of graphics compute units and the graphics processor pipeline. The one or more neural network hardware blocks include hardware to perform neural network operations and activation operations for a layer of a neural network. The programmable neural network unit can configure settings of one or more hardware blocks within the graphics processor pipeline based on a machine learning model trained to optimize performance of a set of workloads.Type: ApplicationFiled: August 9, 2019Publication date: February 13, 2020Applicant: Intel CorporationInventors: HUGUES LABBE, DARREL PALKE, SHERINE ABDELHAK, JILL BOYCE, VARGHESE GEORGE, SCOTT JANUS, ADAM LAKE, ZHIJUN LEI, ZHENGMIN LI, MIKE MACPHERSON, CARL MARSHALL, SELVAKUMAR PANNEER, PRASOONKUMAR SURTI, KARTHIK VEERAMANI, DEEPAK VEMBAR, VALLABHAJOSYULA SRINIVASA SOMAYAZULU
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Publication number: 20190362461Abstract: Embodiments described herein provide a method comprises constructing an application tool profile from a history of tools used by an application to create one or more documents, storing the application tool profile in a memory; and creating a customized application toolset for the application using the application tool profile. Other embodiments may be described and claimed.Type: ApplicationFiled: August 9, 2019Publication date: November 28, 2019Applicant: Intel CorporationInventors: VARGHESE GEORGE, JILL BOYCE, SELVAKUMAR PANNEER, DEEPAK VEMBAR, KARTHIK VEERAMANI, PRASOONKUMAR SURTI, SCOTT JANUS, SOETHIHA SOE, NILESH JAIN, SAURABH TANGRI, GLEN J. ANDERSON, ADAM LAKE, CARL MARSHALL
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Publication number: 20190130639Abstract: Embodiments are directed to neural network processing for multi-object three-dimensional (3D) modeling. An embodiment of a computer-readable storage medium includes executable computer program instructions for obtaining data from multiple cameras, the data including multiple images, and generating a 3D model for 3D imaging based at least in part on the data from the cameras, wherein generating the 3D model includes one or more of performing processing with a first neural network to determine temporal direction based at least in part on motion of one or more objects identified in an image of the multiple images or performing processing with a second neural network to determine semantic content information for an image of the multiple images.Type: ApplicationFiled: December 27, 2018Publication date: May 2, 2019Applicant: Intel CorporationInventors: Jill Boyce, Soethiha Soe, Selva Panneer, Adam Lake, Nilesh Jain, Deepak Vembar, Glen J. Anderson, Varghese George, Carl Marshall, Scott Janus, Saurabh Tangri, Karthik Veeramani, Prasoonkumar Surti
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Patent number: 7561993Abstract: In some embodiments, a method is provided. A sinusoidal signal is generated that is representative of a wave at an average surface of a liquid. A distance between the average surface of the liquid and a bottom of the liquid is determined. A characteristic of the sinusoidal signal is adjusted as a function of the distance.Type: GrantFiled: December 30, 2005Date of Patent: July 14, 2009Assignee: Intel CorporationInventor: Adam Lake
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Publication number: 20070151336Abstract: In some embodiments, a method is provided. A sinusoidal signal is generated that is representative of a wave at an average surface of a liquid. A distance between the average surface of the liquid and a bottom of the liquid is determined. A characteristic of the sinusoidal signal is adjusted as a function of the distance.Type: ApplicationFiled: December 30, 2005Publication date: July 5, 2007Inventor: Adam Lake
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Publication number: 20070002044Abstract: A system and method to provide a hierarchical stencil buffer, the method including creating, for a light source of a graphics scene, a hierarchical stencil buffer (HSB) to store stencil values relative to the light source for a plurality of hierarchical levels of pixels, and storing the stencil values in the HSB in a compressed state. In some embodiments, a shadow test may be performed on a pixel to determine whether the pixel is in shadow relative to the light source, wherein the determining references a stored stencil value for a first hierarchical level in the HSB.Type: ApplicationFiled: June 30, 2005Publication date: January 4, 2007Inventors: Adam Lake, Dean Macri
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Publication number: 20060101434Abstract: A method, apparatus, and system are provided for reducing register file bandwidth using bypass logic control. According to one embodiment, a source code is translated into an intermediate code, which is then to be translated into an executable code. A bypass control logic description file is accessed to perform a lookup of description information at the description file. The description information is then used to compile the intermediate code into the executable.Type: ApplicationFiled: September 30, 2004Publication date: May 11, 2006Inventors: Adam Lake, Chris Wilkerson, Carl Marshall, Daniel Johnston
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Publication number: 20060044313Abstract: A system may include a graphics memory, a data bus, a processor, and a vertex shader. The data bus may be operatively connected to the graphics memory. The processor may send vertex data to the graphics memory via the data bus. The vertex shader may read the vertex data from the graphics memory and may subdivide the vertex data into subdivided vertex data. The vertex shader may also write the subdivided vertex data to the graphics memory.Type: ApplicationFiled: August 26, 2004Publication date: March 2, 2006Inventors: Adam Lake, Carl Marshall
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Publication number: 20050195209Abstract: Colors are obtained and used to shade two-dimensional non-photo realistic images of three-dimensional models. The colors are stored as texels in texture maps. The texels are chosen to shade the images based on their orientation in a scene. The colors may be obtained once, in a pre-rendering process. The colors may then be selected in a run-time process.Type: ApplicationFiled: April 29, 2005Publication date: September 8, 2005Inventors: Adam Lake, Michael Rosenzweig, Mark Harris, Jason Plumb, Carl Marshall