Abstract: A semiconductor device may be created using multiple metal layers and a layer including programmable vias that may be used to form various patterns of interconnections among segments of metal layers. The programmable vias may be formed of materials whose resistance is changeable between a high-resistance state and a low-resistance state.

Abstract: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and/or a microprocessor with customizable I/O, which may be used for configuring and testing the array, where the customizations are all done on a single via layer.

Abstract: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.

Abstract: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations may all be done on a single via layer.

Abstract: A semiconductor device may be created using multiple metal layers and a layer including programmable vias that may be used to form various patterns of interconnections among segments of metal layers. The programmable vias may be formed of materials whose resistance is changeable between a high-resistance state and a low-resistance state.

Abstract: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations may all be done on a single via layer.

Abstract: A configurable logic array composed of: a multiplicity of logic cells, each containing look-up tables, a multiplicity of customizable I/O cells, each containing a multiplicity of pads; and a customizable via connection layer for customizing the cells and interconnect between them, may be constructed to include the option of customizing the I/O cells to act as power or ground pins. Assigning custom power and ground pins may depend on the types of I/O cells and package bonding options.

Abstract: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.

Abstract: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and/or a microprocessor with customizable I/O, which may be used for configuring and testing the array, where the customizations are all done on a single via layer.

Abstract: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.

Abstract: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.

Abstract: A system and method that enables a user to design and use an Integrated Circuit (IC) simulation model without having access to confidential information contained within the model. In one embodiment the system includes a secure section where confidential simulation model information is contained and accessed. The user does not have access to this secure section. The user is provided access to the system via a user-interaction section, which provides controlled access to the IC model. The user can then establish and initiate simulations of the IC model, selecting test stimulus associated with the cores used within the IC model.

Abstract: A method and apparatus for displaying video data on a computer display. Video data is digitized at a video rate and displayed at a different (higher) rate. The digitized video data is provided to the computer memory along with the computer-generated display data. Thus, the video data is part of the windowing environment and can be manipulated like any other window on the display screen. The video data can be arbitrarily sized and is not limited by the input format. The video input is provided to the computer system as a video stream. Next, the video data is resampled and converted from, e.g., the NTSC standard 640.times.480 array into an N.times.M array where N is less than or equal to 640, and M is less than or equal to 480. The video data is then selectively stored in the computer memory with the computer display data by referencing a bit map in the computer memory, producing a region of pixel data that is fully compatible with other windows in the windowing environment.

Abstract: A method and apparatus for a processor or other system device to map processor words to an associated random access memory. In one case, processor words are mapped directly to RAM with no modification. In another case, 32-bit pixels (eight bits each of red, green, blue and alpha) are converted to or from 16-bit pixels (four bits each of red, green, blue and alpha) using an ordered dithering technique. The ordered dithering technique spatially distributes the information that would otherwise be lost by truncation. This is accomplished by replacing exact pixel values with their pseudo-random average. This reduces the required pixel storage requirements by half, while maintaining a higher image quality than would be achieved by truncation alone.