Abstract: Among the embodiments of the present invention, one of the embodiment thereof includes a heterogeneous, high-performance, scalable processor including at least one W-type sub-processor capable of processing W bits, or more, in parallel, W being an integer value, at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value wherein and smaller than W, a shared bus coupling the at least one W-type sub-processor and at least one N-type sub-processor; and at least one Galois Field (GF) MAC coupled to communicate with the W-type sub-processor and the N-type sub-processor, wherein the W-type sub-processor rearranges bytes in transit to or from memory to accommodate execution of applications allowing for fast operations.