Patents by Inventor Adam M. Pyzyna
Adam M. Pyzyna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11737373Abstract: A superconducting device which includes a substrate, multiple niobium leads formed on the substrate, a niobium silicide (NbSix) passivation layer formed on a surface of at least one of the multiple niobium leads, and an aluminum lead formed directly on at least a portion of the NbSix passivation layer such that an interface therebetween is substantially free of oxygen and oxidized material, where the multiple niobium leads and the aluminum lead are constructed to carry a supercurrent while in use.Type: GrantFiled: September 30, 2020Date of Patent: August 22, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew W. Copel, James B. Hannon, Adam M. Pyzyna
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Publication number: 20220102614Abstract: A superconducting device which includes a substrate, multiple niobium leads formed on the substrate, a niobium silicide (NbSix) passivation layer formed on a surface of at least one of the multiple niobium leads, and an aluminum lead formed directly on at least a portion of the NbSix passivation layer such that an interface therebetween is substantially free of oxygen and oxidized material, where the multiple niobium leads and the aluminum lead are constructed to carry a supercurrent while in use.Type: ApplicationFiled: September 30, 2020Publication date: March 31, 2022Inventors: Matthew W. Copel, James B. Hannon, Adam M. Pyzyna
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Patent number: 11221310Abstract: A method for forming a nanogap includes forming a knockoff feature on a dielectric layer and forming a trench in the dielectric layer on opposite sides of the knockoff feature. A noble metal is deposited in the trenches and over the knockoff feature. A top surface is polished to level the noble metal in the trenches with a top of the dielectric layer to form electrodes in the trenches and to remove the noble metal from the knockoff feature. A nanochannel is etched into the dielectric layer such that the knockoff feature is positioned within the nanochannel. The knockoff feature is removed to form a nanogap between the electrodes.Type: GrantFiled: October 31, 2018Date of Patent: January 11, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Adam M. Pyzyna, Joshua T. Smith, Benjamin H. Wunsch
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Patent number: 10600656Abstract: A process for forming patterned copper lines, a pattern of copper lines, and an electronic device having patterned copper lines and at least one CMOS circuit. The process includes assembling an etch stack, wherein the etch stack includes a resist and a copper substrate. The process also includes lithographically patterning the resist to produce a template, and forming a patterned block copolymer mask layer by directed self-assembly. Additionally, the process includes etching portions of the block copolymer mask layer to produce a patterned block copolymer mask layer, and transferring a pattern formed by the template and the patterned block copolymer mask layer to the copper substrate to form the patterned copper lines.Type: GrantFiled: November 21, 2017Date of Patent: March 24, 2020Assignee: International Business Machines CorporationInventors: Eric A. Joseph, Hiroyuki Miyazoe, Adam M. Pyzyna, HsinYu Tsai
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Publication number: 20190393413Abstract: CMOS-compatible non-filamentary RRAM devices and techniques for formation thereof are provided. In one aspect, a method of forming a non-filamentary RRAM device includes: depositing a base oxide layer (e.g., hafnium oxide) on a bottom electrode; depositing a cap layer (e.g., amorphous silicon) on the base oxide layer; and depositing a top electrode on the cap layer, wherein the cap layer and the top electrode are deposited in-situ without any air exposure in between such that there is an absence of oxide at an interface between the cap layer and the top electrode. A low resistivity layer can optionally be deposited on the top electrode. An RRAM device and a computing device having a crossbar array of the present RRAM cells are also provided.Type: ApplicationFiled: June 26, 2018Publication date: December 26, 2019Inventors: Takashi Ando, Eduard A. Cartier, Adam M. Pyzyna, John Bruley
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Patent number: 10505112Abstract: CMOS-compatible non-filamentary RRAM devices and techniques for formation thereof are provided. In one aspect, a method of forming a non-filamentary RRAM device includes: depositing a base oxide layer (e.g., hafnium oxide) on a bottom electrode; depositing a cap layer (e.g., amorphous silicon) on the base oxide layer; and depositing a top electrode on the cap layer, wherein the cap layer and the top electrode are deposited in-situ without any air exposure in between such that there is an absence of oxide at an interface between the cap layer and the top electrode. A low resistivity layer can optionally be deposited on the top electrode. An RRAM device and a computing device having a crossbar array of the present RRAM cells are also provided.Type: GrantFiled: June 26, 2018Date of Patent: December 10, 2019Assignee: International Business Machines CorporationInventors: Takashi Ando, Eduard A. Cartier, Adam M. Pyzyna, John Bruley
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Patent number: 10332957Abstract: A layered structure including a tri-stack dielectric layer and a plurality of metal layers insulated from each other by the tri-stack dielectric layer. The plurality of metal layers includes a set of first-type metal layers and a set of second-type metal layers. An adjacent pair of the plurality of metal layers includes a first-type metal layer and a second-type metal layer. The tri-stack dielectric layer includes a first tri-stack layer including Al2O3, a second tri-stack layer including HfO2; and a third tri-stack layer including Al2O3.Type: GrantFiled: June 30, 2016Date of Patent: June 25, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Takashi Ando, Eduard A. Cartier, Vijay Narayanan, Adam M. Pyzyna
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Publication number: 20190157106Abstract: A process for forming patterned copper lines, a pattern of copper lines, and an electronic device having patterned copper lines and at least one CMOS circuit. The process includes assembling an etch stack, wherein the etch stack includes a resist and a copper substrate. The process also includes lithographically patterning the resist to produce a template, and forming a patterned block copolymer mask layer by directed self-assembly. Additionally, the process includes etching portions of the block copolymer mask layer to produce a patterned block copolymer mask layer, and transferring a pattern formed by the template and the patterned block copolymer mask layer to the copper substrate to form the patterned copper lines.Type: ApplicationFiled: November 21, 2017Publication date: May 23, 2019Inventors: Eric A. Joseph, Hiroyuki Miyazoe, Adam M. Pyzyna, HsinYu Tsai
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Publication number: 20190072518Abstract: A method for forming a nanogap includes forming a knockoff feature on a dielectric layer and forming a trench in the dielectric layer on opposite sides of the knockoff feature. A noble metal is deposited in the trenches and over the knockoff feature. A top surface is polished to level the noble metal in the trenches with a top of the dielectric layer to form electrodes in the trenches and to remove the noble metal from the knockoff feature. A nanochannel is etched into the dielectric layer such that the knockoff feature is positioned within the nanochannel. The knockoff feature is removed to form a nanogap between the electrodes.Type: ApplicationFiled: October 31, 2018Publication date: March 7, 2019Inventors: Adam M. Pyzyna, Joshua T. Smith, Benjamin H. Wunsch
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Patent number: 10168299Abstract: A method for forming a nanogap includes forming a knockoff feature on a dielectric layer and forming a trench in the dielectric layer on opposite sides of the knockoff feature. A noble metal is deposited in the trenches and over the knockoff feature. A top surface is polished to level the noble metal in the trenches with a top of the dielectric layer to form electrodes in the trenches and to remove the noble metal from the knockoff feature. A nanochannel is etched into the dielectric layer such that the knockoff feature is positioned within the nanochannel. The knockoff feature is removed to form a nanogap between the electrodes.Type: GrantFiled: July 15, 2016Date of Patent: January 1, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Adam M. Pyzyna, Joshua T. Smith, Benjamin H. Wunsch
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Patent number: 10068850Abstract: A modified trench metal-semiconductor alloy formation method involves depositing a layer of a printable dielectric or a sacrificial carbon material within a trench structure and over contact regions of a semiconductor device, and then selectively removing the printable dielectric or sacrificial carbon material to segment the trench and form plural contact vias. A metallization layer is formed within the contact vias and over the contact regions.Type: GrantFiled: July 28, 2017Date of Patent: September 4, 2018Assignee: International Business Machines CorporationInventors: Josephine B. Chang, Michael A. Guillorn, Fei Liu, Adam M. Pyzyna
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Patent number: 10014214Abstract: An electronic device is provided. The electronic device includes a semiconductor layer, a dielectric layer disposed on the semiconductor layer, circuitry disposed on the dielectric layer that includes interconnected cells, first contact line metallization and second contact line metallization, first power metallization disposed in-plane with or above the circuitry and second power metallization disposed in a trench defined in at least the dielectric layer. The electronic device further includes insulation disposed to insulate the second power metallization from the circuitry and the first power metallization at first locations and to permit electrical communication between the second power metallization, the circuitry and the first power metallization at second locations.Type: GrantFiled: May 12, 2017Date of Patent: July 3, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Josephine B. Chang, Leland Chang, Michael A. Guillorn, Chung-Hsun Lin, Adam M. Pyzyna
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Publication number: 20180017524Abstract: A method for forming a nanogap includes forming a knockoff feature on a dielectric layer and forming a trench in the dielectric layer on opposite sides of the knockoff feature. A noble metal is deposited in the trenches and over the knockoff feature. A top surface is polished to level the noble metal in the trenches with a top of the dielectric layer to form electrodes in the trenches and to remove the noble metal from the knockoff feature. A nanochannel is etched into the dielectric layer such that the knockoff feature is positioned within the nanochannel. The knockoff feature is removed to form a nanogap between the electrodes.Type: ApplicationFiled: July 15, 2016Publication date: January 18, 2018Inventors: Adam M. Pyzyna, Joshua T. Smith, Benjamin H. Wunsch
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Publication number: 20180006108Abstract: A layered structure including a tri-stack dielectric layer and a plurality of metal layers insulated from each other by the tri-stack dielectric layer. The plurality of metal layers includes a set of first-type metal layers and a set of second-type metal layers. An adjacent pair of the plurality of metal layers includes a first-type metal layer and a second-type metal layer. The tri-stack dielectric layer includes a first tri-stack layer including Al2O3, a second tri-stack layer including HfO2; and a third tri-stack layer including Al2O3.Type: ApplicationFiled: June 30, 2016Publication date: January 4, 2018Inventors: Takashi Ando, Eduard A. Cartier, Vijay Narayanan, Adam M. Pyzyna
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Publication number: 20170330830Abstract: A modified trench metal-semiconductor alloy formation method involves depositing a layer of a printable dielectric or a sacrificial carbon material within a trench structure and over contact regions of a semiconductor device, and then selectively removing the printable dielectric or sacrificial carbon material to segment the trench and form plural contact vias. A metallization layer is formed within the contact vias and over the contact regions.Type: ApplicationFiled: July 28, 2017Publication date: November 16, 2017Inventors: Josephine B. Chang, Michael A. Guillorn, Fei Liu, Adam M. Pyzyna
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Publication number: 20170250111Abstract: An electronic device is provided. The electronic device includes a semiconductor layer, a dielectric layer disposed on the semiconductor layer, circuitry disposed on the dielectric layer that includes interconnected cells, first contact line metallization and second contact line metallization, first power metallization disposed in-plane with or above the circuitry and second power metallization disposed in a trench defined in at least the dielectric layer. The electronic device further includes insulation disposed to insulate the second power metallization from the circuitry and the first power metallization at first locations and to permit electrical communication between the second power metallization, the circuitry and the first power metallization at second locations.Type: ApplicationFiled: May 12, 2017Publication date: August 31, 2017Inventors: Josephine B. Chang, Leland Chang, Michael A. Guillorn, Chung-Hsun Lin, Adam M. Pyzyna
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Patent number: 9721888Abstract: A modified trench metal-semiconductor alloy formation method involves depositing a layer of a printable dielectric or a sacrificial carbon material within a trench structure and over contact regions of a semiconductor device, and then selectively removing the printable dielectric or sacrificial carbon material to segment the trench and form plural contact vias. A metallization layer is formed within the contact vias and over the contact regions.Type: GrantFiled: December 8, 2015Date of Patent: August 1, 2017Assignee: International Business Machines CorporationInventors: Josephine B. Chang, Michael A. Guillorn, Fei Liu, Adam M. Pyzyna
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Patent number: 9716036Abstract: An electronic device is provided. The electronic device includes a semiconductor layer, a dielectric layer disposed on the semiconductor layer, circuitry disposed on the dielectric layer that includes interconnected cells, first contact line metallization and second contact line metallization, first power metallization disposed in-plane with or above the circuitry and second power metallization disposed in a trench defined in at least the dielectric layer. The electronic device further includes insulation disposed to insulate the second power metallization from the circuitry and the first power metallization at first locations and to permit electrical communication between the second power metallization, the circuitry and the first power metallization at second locations.Type: GrantFiled: June 8, 2015Date of Patent: July 25, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Josephine B. Chang, Leland Chang, Michael A. Guillorn, Chung-Hsun Lin, Adam M. Pyzyna
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Publication number: 20170162496Abstract: A modified trench metal-semiconductor alloy formation method involves depositing a layer of a printable dielectric or a sacrificial carbon material within a trench structure and over contact regions of a semiconductor device, and then selectively removing the printable dielectric or sacrificial carbon material to segment the trench and form plural contact vias. A metallization layer is formed within the contact vias and over the contact regions.Type: ApplicationFiled: December 8, 2015Publication date: June 8, 2017Inventors: Josephine B. Chang, Michael A. Guillorn, Fei Liu, Adam M. Pyzyna
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Patent number: 9653679Abstract: A method of making a magnetoresistive structure is disclosed. The method includes forming a pillar structure including a magnetic tunnel junction on a substrate that includes a first electrode, depositing a stressed layer onto a pillar structure sidewall, and depositing a second electrode above the magnetic tunnel junction.Type: GrantFiled: May 24, 2016Date of Patent: May 16, 2017Assignee: International Business Machines CorporationInventors: Anthony J. Annunziata, Chandrasekharan Kothandaraman, Gen P. Lauer, Adam M. Pyzyna