Patents by Inventor Adam Michael Espeseth

Adam Michael Espeseth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11226747
    Abstract: Techniques for improved copy on write functionality within an SSD are disclosed. In some embodiments, the techniques may be realized as a method for providing improved copy on write functionality within an SSD including providing, in memory of a device, an indirection data structure. The data structure may include a master entry for cloned data, the master entry having a reference to one or more indexes and a clone entry for the cloned data, the cloned entry having at least one of: a reference to a master index, a reference to a next index, and a value indicating an end of a data structure. The techniques may include traversing, using a computer processor, one or more copies of the cloned data using one or more of the references.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: January 18, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Dylan Mark Dewitt, Adam Michael Espeseth, Colin Christopher McCambridge, David George Dreyer
  • Publication number: 20200150883
    Abstract: Techniques for improved copy on write functionality within an SSD are disclosed. In some embodiments, the techniques may be realized as a method for providing improved copy on write functionality within an SSD including providing, in memory of a device, an indirection data structure. The data structure may include a master entry for cloned data, the master entry having a reference to one or more indexes and a clone entry for the cloned data, the cloned entry having at least one of: a reference to a master index, a reference to a next index, and a value indicating an end of a data structure. The techniques may include traversing, using a computer processor, one or more copies of the cloned data using one or more of the references.
    Type: Application
    Filed: January 17, 2020
    Publication date: May 14, 2020
    Applicant: Western Digital Technologies, Inc.
    Inventors: Dylan Mark DEWITT, Adam Michael ESPESETH, Colin Christopher MCCAMBRIDGE, David George DREYER
  • Patent number: 10540106
    Abstract: Techniques for improved copy on write functionality within an SSD are disclosed. In some embodiments, the techniques may be realized as a method for providing improved copy on write functionality within an SSD including providing, in memory of a device, an indirection data structure. The data structure may include a master entry for cloned data, the master entry having a reference to one or more indexes and a clone entry for the cloned data, the cloned entry having at least one of: a reference to a master index, a reference to a next index, and a value indicating an end of a data structure. The techniques may include traversing, using a computer processor, one or more copies of the cloned data using one or more of the references.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: January 21, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Dylan Mark Dewitt, Adam Michael Espeseth, Colin Christopher Mccambridge, David George Dreyer
  • Patent number: 10474618
    Abstract: A method, apparatus, and system are provided for implementing debug data saving in host memory on a Peripheral Component Interconnect Express (PCIE) solid state drive (SSD). Upon Power Loss Interruption (PLI) event detected in a solid state drive (SSD), the SSD transfers debug data directly to the host system main (DRAM) memory via a Peripheral Component Interconnect Express (PCIE) bus.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: November 12, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Michael J. Anderson, Adam Michael Espeseth, Brandon William Schulz, Lee Anton Sendelbach
  • Patent number: 10235069
    Abstract: A method and apparatus for accessing a storage device is disclosed. More specifically, for load balancing by dynamically transferring memory address range assignments. In one embodiment, a storage device receives, from a host apparatus, an access request directed at two or more storage addresses, assigns, based on a first storage address of the two or more storage addresses, the access request to a first processor of two or more processors of the storage device, obtains a local memory lock based on the first storage address, determines, based on a second storage address of the two or more storage addresses, that the second storage address is assigned to a second processor of the two or more processors, obtains a remote memory lock from the second processor based on the second storage address and processes the access request.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: March 19, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Adam Michael Espeseth, Brent William Jacobs
  • Patent number: 10108350
    Abstract: An apparatus for implementing an enhanced-write-bandwidth caching stream includes a memory that stores machine instructions and a processor that executes the machine instructions. The apparatus apportions a first address space and a second address space that comprises a logical namespace. The apparatus also subjects the first address space to host-write throttling, and exempts the second address space from host-write throttling. The apparatus further requires that valid data in memory cells corresponding to the second address space be invalidated at an interval not to exceed a number of host writes equaling the capacity of the second address space.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: October 23, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Adam Michael Espeseth, Colin Christopher McCambridge, David George Dreyer
  • Patent number: 10048876
    Abstract: An apparatus for implementing an enhanced-write-bandwidth caching stream includes a memory that stores machine instructions and a processor that executes the machine instructions. The apparatus receives a first host write stream and a second host write stream that comprises latency-sensitive host write requests. The apparatus also subjects the first host write stream to host-write throttling, and exempts the second host write stream from host-write throttling. The apparatus further requires that the second host write stream invalidate logical blocks in an order corresponding to a previous order in which the respective logical blocks were previously programmed.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: August 14, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Adam Michael Espeseth, Colin Christopher McCambridge, David George Dreyer
  • Publication number: 20180181328
    Abstract: A method and apparatus for accessing a storage device is disclosed. More specifically, for load balancing by dynamically transferring memory address range assignments. In one embodiment, a storage device receives, from a host apparatus, an access request directed at two or more storage addresses, assigns, based on a first storage address of the two or more storage addresses, the access request to a first processor of two or more processors of the storage device, obtains a local memory lock based on the first storage address, determines, based on a second storage address of the two or more storage addresses, that the second storage address is assigned to a second processor of the two or more processors, obtains a remote memory lock from the second processor based on the second storage address and processes the access request.
    Type: Application
    Filed: December 22, 2016
    Publication date: June 28, 2018
    Inventors: Adam Michael ESPESETH, Brent William JACOBS
  • Publication number: 20180150249
    Abstract: Techniques for improved copy on write functionality within an SSD are disclosed. In some embodiments, the techniques may be realized as a method for providing improved copy on write functionality within an SSD including providing, in memory of a device, an indirection data structure. The data structure may include a master entry for cloned data, the master entry having a reference to one or more indexes and a clone entry for the cloned data, the cloned entry having at least one of: a reference to a master index, a reference to a next index, and a value indicating an end of a data structure. The techniques may include traversing, using a computer processor, one or more copies of the cloned data using one or more of the references.
    Type: Application
    Filed: January 22, 2018
    Publication date: May 31, 2018
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Dylan Mark DEWITT, Adam Michael ESPESETH, Colin Christopher MCCAMBRIDGE, David George DREYER
  • Patent number: 9880755
    Abstract: Techniques for improved copy on write functionality within an SSD are disclosed. In some embodiments, the techniques may be realized as a method for providing improved copy on write functionality within an SSD including providing, in memory of a device, an indirection data structure. The data structure may include a master entry for cloned data, the master entry having a reference to one or more indexes and a clone entry for the cloned data, the cloned entry having at least one of: a reference to a master index, a reference to a next index, and a value indicating an end of a data structure. The techniques may include traversing, using a computer processor, one or more copies of the cloned data using one or more of the references.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: January 30, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Dylan Mark Dewitt, Adam Michael Espeseth, Colin Christopher McCambridge, David George Dreyer
  • Publication number: 20170075590
    Abstract: An apparatus for implementing an enhanced-write-bandwidth caching stream includes a memory that stores machine instructions and a processor that executes the machine instructions. The apparatus apportions a first address space and a second address space that comprises a logical namespace. The apparatus also subjects the first address space to host-write throttling, and exempts the second address space from host-write throttling. The apparatus further requires that valid data in memory cells corresponding to the second address space be invalidated at an interval not to exceed a number of host writes equaling the capacity of the second address space.
    Type: Application
    Filed: September 10, 2015
    Publication date: March 16, 2017
    Inventors: Adam Michael ESPESETH, Colin Christopher McCAMBRIDGE, David George DREYER
  • Publication number: 20170075591
    Abstract: An apparatus for implementing an enhanced-write-bandwidth caching stream includes a memory that stores machine instructions and a processor that executes the machine instructions. The apparatus receives a first host write stream and a second host write stream that comprises latency-sensitive host write requests. The apparatus also subjects the first host write stream to host-write throttling, and exempts the second host write stream from host-write throttling. The apparatus further requires that the second host write stream invalidate logical blocks in an order corresponding to a previous order in which the respective logical blocks were previously programmed.
    Type: Application
    Filed: September 10, 2015
    Publication date: March 16, 2017
    Inventors: Adam Michael ESPESETH, Colin Christopher McCAMBRIDGE, David George DREYER
  • Publication number: 20160246521
    Abstract: Techniques for improved copy on write functionality within an SSD are disclosed. In some embodiments, the techniques may be realized as a method for providing improved copy on write functionality within an SSD including providing, in memory of a device, an indirection data structure. The data structure may include a master entry for cloned data, the master entry having a reference to one or more indexes and a clone entry for the cloned data, the cloned entry having at least one of: a reference to a master index, a reference to a next index, and a value indicating an end of a data structure. The techniques may include traversing, using a computer processor, one or more copies of the cloned data using one or more of the references.
    Type: Application
    Filed: February 25, 2015
    Publication date: August 25, 2016
    Applicant: HGST Netherlands B.V.
    Inventors: Dylan Mark DEWITT, Adam Michael ESPESETH, Colin Christopher MCCAMBRIDGE, David George DREYER
  • Publication number: 20160070486
    Abstract: A method, apparatus, and system are provided for implementing debug data saving in host memory on a Peripheral Component Interconnect Express (PCIE) solid state drive (SSD). Upon Power Loss Interruption (PLI) event detected in a solid state drive (SSD), the SSD transfers debug data directly to the host system main (DRAM) memory via a Peripheral Component Interconnect Express (PCIE) bus.
    Type: Application
    Filed: September 4, 2014
    Publication date: March 10, 2016
    Inventors: Michael J. Anderson, Adam Michael Espeseth, Brandon William Schulz, Lee Anton Sendelbach
  • Publication number: 20150178017
    Abstract: An abort function for storage devices sets a “poison bit” flag in the command to be deleted while the command resides on a submission queue prior to being fetched by the SSD controller. In response to the set “poison bit” flag, a storage device controller aborts execution of the I/O command and returns an abort successful status reply to the completion queue.
    Type: Application
    Filed: December 20, 2013
    Publication date: June 25, 2015
    Applicant: HGST Netherlands B.V.
    Inventors: David Lee DARRINGTON, Dylan Mark DEWITT, Adam Michael ESPESETH, Lee Anton SENDELBACH
  • Patent number: 9052835
    Abstract: An abort function for storage devices sets a “poison bit” flag in the command to be deleted while the command resides on a submission queue prior to being fetched by the SSD controller. In response to the set “poison bit” flag, a storage device controller aborts execution of the I/O command and returns an abort successful status reply to the completion queue.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: June 9, 2015
    Assignee: HGST NETHERLANDS B.V.
    Inventors: David Lee Darrington, Dylan Mark Dewitt, Adam Michael Espeseth, Lee Anton Sendelbach
  • Patent number: 8250380
    Abstract: A method and apparatus are provided for implementing secure erase for solid state drives (SSDs). An encryption key is used to encrypt data being written to SSD. A controller identifies a key storage option, and responsive to the identified key storage option, stores a key for data encryption and decryption. The controller deletes the key within the SSD responsive to the identified key storage option, ensuring that once the key is deleted, the key is not recoverable and data is effectively erased.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: August 21, 2012
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Cyril Guyot, Zvonimir Z. Bandic, Yuval Cassuto, Adam Michael Espeseth, Marco Sanvido
  • Publication number: 20110154060
    Abstract: A method and apparatus are provided for implementing secure erase for solid state drives (SSDs). An encryption key is used to encrypt data being written to SSD. A controller identifies a key storage option, and responsive to the identified key storage option, stores a key for data encryption and decryption. The controller deletes the key within the SSD responsive to the identified key storage option, ensuring that once the key is deleted, the key is not recoverable and data is effectively erased.
    Type: Application
    Filed: December 17, 2009
    Publication date: June 23, 2011
    Applicant: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Cyril Guyot, Zvonimir Z. Bandic, Yuval Cassuto, Adam Michael Espeseth, Marco Sanvido
  • Patent number: 7526605
    Abstract: Multiple disk access commands such as XOR commands are broken down into their constituent read and write parts and, if in LBA sequence, coalesced into pipes. These XOR read and write commands are then provided to the RPO algorithm of the HDD for scheduling along with data reads and writes. The actual XOR buffer operation is also scheduled by the RPO algorithm, advantageously to occur during a seek for another read or write.
    Type: Grant
    Filed: April 29, 2005
    Date of Patent: April 28, 2009
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Adam Michael Espeseth, Edward Henry Younk
  • Patent number: 7376784
    Abstract: Commands in a queue in a hard disk drive (HDD) are selected based on a benefit of providing either an optimized throughput or an optimized number of commands per second execution, as opposed to a simple shortest access time first (SATF) selection method.
    Type: Grant
    Filed: January 26, 2004
    Date of Patent: May 20, 2008
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Adam Michael Espeseth, Robert Anton Steinbach, Trevor James Briggs