Abstract: Ring packet built-in self-test (PBIST) circuitry configured to detect errors in wires connecting a ring of superconducting chips includes circuitry configured to make the PBIST immune to interchip latency and still allow the PBIST to test a stop-to-stop connection. By making a PBIST independent of latency, an entire ring can be characterized for latency and for its bit-error rate prior to running any functional test. Such systems and associated methods can be scaled to larger platforms having any number of ring stops. The PBIST circuitry can function as either transmitter or receiver, or both, to test an entire ring. The PBIST can also be used to tune clocks in the ring to achieve the lowest overall bit error rate (BER) in the ring.

Abstract: Ring packet built-in self-test (PBIST) circuitry configured to detect errors in wires connecting a ring of superconducting chips includes circuitry configured to make the PBIST immune to interchip latency and still allow the PBIST to test a stop-to-stop connection. By making a PBIST independent of latency, an entire ring can be characterized for latency and for its bit-error rate prior to running any functional test. Such systems and associated methods can be scaled to larger platforms having any number of ring stops. The PBIST circuitry can function as either transmitter or receiver, or both, to test an entire ring. The PBIST can also be used to tune clocks in the ring to achieve the lowest overall bit error rate (BER) in the ring.

Abstract: Methods, apparatus, and computer-readable storage media are disclosed for applying filtering operations to data transferred as part of a direct memory access (DMA) operation. In one example of the disclosed technology, a system includes a processor, memory, and a direct memory access (DMA) engine coupled to the memory for reading a set of data from a selected range of read memory addresses for the memory without using the processor. A line buffer coupled to the DMA engine is configured to receive DMA read data and temporarily store a portion, but not all of the data set being read by the DMA engine in a line buffer. A digital filter is configured to apply a filtering operation to a windowed subset of the buffered portion of the data set, producing filtered data that is stored to a selected range of write memory addresses for the memory, without using the processor.

Abstract: Methods, apparatus, and computer-readable storage media are disclosed for applying filtering operations to data transferred as part of a direct memory access (DMA) operation. In one example of the disclosed technology, a system includes a processor, memory, and a direct memory access (DMA) engine coupled to the memory for reading a set of data from a selected range of read memory addresses for the memory without using the processor. A line buffer coupled to the DMA engine is configured to receive DMA read data and temporarily store a portion, but not all of the data set being read by the DMA engine in a line buffer. A digital filter is configured to apply a filtering operation to a windowed subset of the buffered portion of the data set, producing filtered data that is stored to a selected range of write memory addresses for the memory, without using the processor.

Abstract: A high speed computer processor system has a high speed interface for a graphics processor. A preferred embodiment combines a PowerPC microprocessor called the Giga-Processor Ultralite (GPUL) 110 from International Business Machines Corporation (IBM) with a high speed interface on a multi-chip module.