Patents by Inventor Adam P. Burns
Adam P. Burns has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8868034Abstract: Embodiments may comprise logic such as hardware and/or code to provide a secure device area network. Many embodiments comprise a gateway node or enterprise enhanced node with a services distribution frame installed on a customer's premises. The gateway node or enterprise enhanced node may interconnect the secure wireless device area network at the customer's premises with a cellular network. In many embodiments, the cellular network core may provision authentication credentials and security keys, and manage access polies to facilitate access by Application Service Providers to devices on premises including smart devices via a security and policy enforcement function of a services distribution frame of the gateway node or enterprise enhanced node, Authorized members of the secure wireless device area network may connect to the Wide Area Network (WAN) through the gateway node and the cellular network core.Type: GrantFiled: December 25, 2010Date of Patent: October 21, 2014Assignee: Intel CorporationInventors: Rakesh Dodeja, Ashok Sunder Rajan, Kevin D. Johnson, Martin Mcdonnell, William J. Tiso, Todd A. Keaffaber, Adam P. Burns
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Patent number: 8250338Abstract: A mechanism for broadcasting instructions/data to a plurality of processors in a multiprocessor device via aliasing is provided. In order to broadcast data to a plurality of processors, a control processor writes to the registers that store the identifiers of the processors and sets two or more of these registers to a same value. The control processor may write the desired data/instructions to be broadcast to a portion of memory corresponding to the starting address associated with the processor identifier of the two or more processors. When the two or more processors look for a starting address of their local store from which to read, the two or more processors will identify the same starting address, essentially aliasing the memory region. The two or more processors will read the instructions/data from the same aliased memory region starting at the identified starting address and process the same instructions/data.Type: GrantFiled: May 29, 2008Date of Patent: August 21, 2012Assignee: International Business Machines CorporationInventors: Adam P. Burns, Steven L. Roberts, Christopher J Spandikow, Todd E. Swanson
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Publication number: 20120164975Abstract: Embodiments may comprise logic such as hardware and/or code to provide a secure device area network. Many embodiments comprise a gateway node or enterprise enhanced node with a services distribution frame installed on a customer's premises. The gateway node or enterprise enhanced node may interconnect the secure wireless device area network at the customer's premises with a cellular network. In many embodiments, the cellular network core may provision authentication credentials and security keys, and manage access polies to facilitate access by Application Service Providers to devices on premises including smart devices via a security and policy enforcement function of a services distribution frame of the gateway node or enterprise enhanced node, Authorized members of the secure wireless device area network may connect to the Wide Area Network (WAN) through the gateway node and the cellular network core.Type: ApplicationFiled: December 25, 2010Publication date: June 28, 2012Inventors: Rakesh Dodeja, Ashok Sunder Rajan, Kevin D. Johnson, Martin Mcdonnell, William J. Tiso, Todd A. Keaffaber, Adam P. Burns
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Patent number: 7730279Abstract: A system for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself. The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the local storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.Type: GrantFiled: April 24, 2009Date of Patent: June 1, 2010Assignee: International Business Machines CorporationInventors: Adam P. Burns, Michael N. Day, Brian Flachs, H. Peter Hofstee, Charles R. Johns, John Liberty
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Publication number: 20090204781Abstract: A system for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself. The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the local storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.Type: ApplicationFiled: April 24, 2009Publication date: August 13, 2009Applicant: International Business Machines CorporationInventors: Adam P. Burns, Michael N. Day, Brian Flachs, H. Peter Hofstee, Charles R. Johns, John Liberty
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Patent number: 7533238Abstract: A method for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the 1ocal storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.Type: GrantFiled: August 19, 2005Date of Patent: May 12, 2009Assignee: International Business Machines CorporationInventors: Adam P. Burns, Michael N. Day, Brian Flachs, H. Peter Hofstee, Charles R. Johns, John Liberty
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Patent number: 7493468Abstract: A method for broadcasting instructions/data to a plurality of processors in a multiprocessor device via aliasing is provided. In order to broadcast data to a plurality of processors, a control processor writes to the registers that store the identifiers of the processors and sets two or more of these registers to a same value. The control processor may write the desired data/instructions to be broadcast to a portion of memory corresponding to the starting address associated with the processor identifier of the two or more processors. When the two or more processors look for a starting address of their local store from which to read, the two or more processors will identify the same starting address, essentially aliasing the memory region. The two or more processors will read the instructions/data from the same aliased memory region starting at the identified starting address and process the same instructions/data.Type: GrantFiled: June 1, 2006Date of Patent: February 17, 2009Assignee: International Business Machines CorporationInventors: Adam P. Burns, Steven L. Roberts, Christopher J. Spandikow, Todd E. Swanson
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Publication number: 20080229051Abstract: A mechanism for broadcasting instructions/data to a plurality of processors in a multiprocessor device via aliasing is provided. In order to broadcast data to a plurality of processors, a control processor writes to the registers that store the identifiers of the processors and sets two or more of these registers to a same value. The control processor may write the desired data/instructions to be broadcast to a portion of memory corresponding to the starting address associated with the processor identifier of the two or more processors. When the two or more processors look for a starting address of their local store from which to read the two or more processors will identify the same starting address, essentially aliasing the memory region. The two or more processors will read the instructions/data from the same aliased memory region starting at the identified starting address and process the same instructions/data.Type: ApplicationFiled: May 29, 2008Publication date: September 18, 2008Applicant: International Business Machines CorporationInventors: Adam P. Burns, Steven L. Roberts, Christopher J. Spandikow, Todd E. Swanson
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Publication number: 20070283037Abstract: A system and method for broadcasting instructions/data to a plurality of processors in a multiprocessor device via aliasing are provided. In order to broadcast data to a plurality of processors, a control processor writes to the registers that store the identifiers of the processors and sets two or more of these registers to a same value. The control processor may write the desired data/instructions to be broadcast to a portion of memory corresponding to the starting address associated with the processor identifier of the two or more processors. When the two or more processors look for a starting address of their local store from which to read, the two or more processors will identify the same starting address, essentially aliasing the memory region. The two or more processors will read the instructions/data from the same aliased memory region starting at the identified starting address and process the same instructions/data.Type: ApplicationFiled: June 1, 2006Publication date: December 6, 2007Inventors: Adam P. Burns, Steven L. Roberts, Christopher J. Spandikow, Todd E. Swanson