Abstract: A non-volatile memory (NVM) system includes a plurality of NVM cells fabricated in a dual-well structure. Each NVM cell includes an access transistor and an NVM transistor, wherein the access transistor has a drain region that is continuous with a source region of the NVM transistor. The drain regions of each NVM transistor in a column of the array are commonly connected to a corresponding bit line. The control gates of each NVM transistor in a row of the array are commonly connected to a corresponding word line. The source regions of each of the access transistors in the array are commonly coupled. The NVM cells are programmed and erased without having to apply the high programming voltage VPP across the gate dielectric layers of the access transistors. As a result, the NVM cells can be scaled down to sub-0.35 micron geometries.

Abstract: A non-volatile memory (NVM) system includes a plurality of NVM cells fabricated in a dual-well structure. Each NVM cell includes an access transistor and an NVM transistor, wherein the access transistor has a drain region that is continuous with a source region of the NVM transistor. The drain regions of each NVM transistor in a column of the array are commonly connected to a corresponding bit line. The control gates of each NVM transistor in a row of the array are commonly connected to a corresponding word line. The source regions of each of the access transistors in the array are commonly coupled. The NVM cells are programmed and erased without having to apply the high programming voltage VPP across the gate dielectric layers of the access transistors. As a result, the NVM cells can be scaled down to sub-0.35 micron geometries.

Abstract: A non-volatile memory (NVM) system includes a plurality of NVM cells fabricated in a dual-well structure. Each NVM cell includes an access transistor and an NVM transistor, wherein the access transistor has a drain region that is continuous with a source region of the NVM transistor. The drain regions of each NVM transistor in a column of the array are commonly connected to a corresponding bit line. The control gates of each NVM transistor in a row of the array are commonly connected to a corresponding word line. The source regions of each of the access transistors in the array are commonly coupled. The NVM cells are programmed and erased without having to apply the high programming voltage VPP across the gate dielectric layers of the access transistors. As a result, the NVM cells can be scaled down to sub-0.35 micron geometries.

Abstract: A digital potentiometer is disclosed that includes first, second, and third signal terminals. A chain of series-connected impedance elements with multiple tap points is connected between the first and second signal terminals. A plurality of first switching devices are each connected to a respective one of the multiple tap points and to an internal wiper node. A configurable output stage is connected between the internal wiper node and the third signal terminal. The configurable output stage includes a buffer and a second switching device. The second switching device is operable to bypass the buffer. A switching circuit controls switching of the first switching devices. The switching circuit includes a Gray-code counter, a Gray-code decoder, and a make-before-break circuit that controls the timing of the switching of the wiper switches.

Abstract: A digital potentiometer, configurable and programmable using nonvolatile memory is disclosed. A unity-gain configured, rail-to-rail operational amplifier, used as voltage follower of buffer, can be inserted, by programming, between an internal wiper terminal and an output terminal of the digital potentiometer. This way, in certain applications, it is possible to take advantage of the low output resistance given by an analog buffer. The operational amplifier can be shutdown and bypassed by a switching device to provide a circuit behavior similar to a digital potentiometer without an output buffer. Using a dual-writing circuitry, first the complemented data, then the data itself, are written in the nonvolatile memory, improving the reliability. A Gray-code counter having a single bit changed at one time and no decode glitch is present. A make-before-break circuitry gives a short overlap conduction time for any adjacent pair of switches; one being turned-off while the other is turned-on.

Abstract: A digital potentiometer is disclosed that includes first, second, and third signal terminals. A chain of series-connected impedance elements with multiple tap points is connected between the first and second signal terminals. A plurality of first switching devices are each connected to a respective one of the multiple tap points and to an internal wiper node. A configurable output stage is connected between the internal wiper node and the third signal terminal. The configurable output stage includes a buffer and a second switching device. The second switching device is operable to bypass the buffer. A switching circuit controls switching of the first switching devices. The switching circuit includes a Gray-code counter, a Gray-code decoder, and a make-before-break circuit that controls the timing of the switching of the wiper switches.

Abstract: A digital potentiometer, configurable and programmable using nonvolatile memory is disclosed. A unity-gain configured, rail-to-rail operational amplifier, used as voltage follower of buffer, can be inserted, by programming, between an internal wiper terminal and an output terminal of the digital potentiometer. This way, in certain applications, it is possible to take advantage of the low output resistance given by an analog buffer. The operational amplifier can be shutdown and bypassed by a switching device to provide a circuit behavior similar to a digital potentiometer without an output buffer. Using a dual-writing circuitry, first the complemented data, then the data itself, are written in the nonvolatile memory, improving the reliability. A Gray-code counter having a single bit changed at one time and no decode glitch is present. A make-before-break circuitry gives a short overlap conduction time for any adjacent pair of switches; one being turned-off while the other is turned-on.