Abstract: Embodiments include methods, processing systems and computer program products for extracting via capacitance. Aspects include placing various shapes of target nets of an IC into a Cshapes collection and a CshapesVia collection, processing the shapes in these collections and placing the processed shapes into a Ctile collection and a CtilesVia collection, and extracting via capacitance of the target nets through each of Cshapes, CshapesVia, Ctiles, and CtilesVia collections. In exemplary embodiments, the processing operation includes: reducing the complexity of the shapes in the shape collections, removing all overhang shapes, and all overlapped shapes from the shape collections, and unioning the shapes in the Cshapes collection and the CshapesVia collection, respectively.

Abstract: Disclosed is a method for improving capacitance extraction performance in a circuit, the method including mapping, via a computing resource, a first layout including a plurality of wiring paths, selecting at least one target wire from the plurality of wiring paths, selecting at least one group of wires running orthogonally to the at least one target wire, identifying and selecting within the at least one group at least one set of two or more wires that are combinable for representation as a single merged wire, mapping a second layout, via the computing resource, and representing the at least one set of two or more wires as the single merged wire in said second layout, analyzing parasitic capacitance between the at least one target wire and the at least one group of wires using the second layout, and manufacturing the circuit using information from the analyzing of parasitic capacitance.

Abstract: A first open path in a microprocessor design is identified. At least one modification to a design of that first open path is simulated. An updated arrival time at a pin is calculated based on the simulated modification or modifications. An updated path time is then calculated based on the updated arrival time.

Abstract: A first open path in a microprocessor design is identified. At least one modification to a design of that first open path is simulated. An updated arrival time at a pin is calculated based on the simulated modification or modifications. An updated path time is then calculated based on the updated arrival time.

Abstract: A method, system and computer-readable medium for reducing repeater power and crosstalk are provided. The method includes generating a model of a circuit including a plurality of original repeaters connected between at least one source and at least one sink, performing a power optimization analysis on the plurality of original repeaters to change the plurality of original repeaters to low-power repeaters based on predetermined optimization parameters, performing a crosstalk analysis on the model of the circuit including the low-power repeaters to determine whether a crosstalk timing violation exists, and changing at least one of the low-power repeaters to a higher-power repeater when it is determined that a crosstalk violation exists, and leaving the low-power repeaters in the model of the circuit when it is determined that a crosstalk violation does not exist.

Abstract: A method, system and computer-readable medium for reducing repeater power and crosstalk are provided. The method includes generating a model of a circuit including a plurality of original repeaters connected between at least one source and at least one sink, performing a power optimization analysis on the plurality of original repeaters to change the plurality of original repeaters to low-power repeaters based on predetermined optimization parameters, performing a crosstalk analysis on the model of the circuit including the low-power repeaters to determine whether a crosstalk timing violation exists, and changing at least one of the low-power repeaters to a higher-power repeater when it is determined that a crosstalk violation exists, and leaving the low-power repeaters in the model of the circuit when it is determined that a crosstalk violation does not exist.

Abstract: A method, system and computer-readable medium for reducing repeater power and crosstalk are provided. The method includes generating a model of a circuit including a plurality of original repeaters connected between at least one source and at least one sink, performing a power optimization analysis on the plurality of original repeaters to change the plurality of original repeaters to low-power repeaters based on predetermined optimization parameters, performing a crosstalk analysis on the model of the circuit including the low-power repeaters to determine whether a crosstalk timing violation exists, and changing at least one of the low-power repeaters to a higher-power repeater when it is determined that a crosstalk violation exists, and leaving the low-power repeaters in the model of the circuit when it is determined that a crosstalk violation does not exist.

Abstract: A method, system and computer-readable medium for reducing repeater power and crosstalk are provided. The method includes generating a model of a circuit including a plurality of original repeaters connected between at least one source and at least one sink, performing a power optimization analysis on the plurality of original repeaters to change the plurality of original repeaters to low-power repeaters based on predetermined optimization parameters, performing a crosstalk analysis on the model of the circuit including the low-power repeaters to determine whether a crosstalk timing violation exists, and changing at least one of the low-power repeaters to a higher-power repeater when it is determined that a crosstalk violation exists, and leaving the low-power repeaters in the model of the circuit when it is determined that a crosstalk violation does not exist.

Abstract: A design structure for reducing coupling between wires of an electronic circuit is proposed, wherein sets of nets are classified according to their coupling characteristics, and spacing between wires assigned to the sets of nets is chosen according to the coupling characteristics.

Abstract: A routing method for reducing coupling between wires of an electronic circuit is proposed, wherein sets of nets are classified according to their coupling characteristics, and spacing between wires assigned to the sets of nets is chosen according to the coupling characteristics.

Abstract: A method, system, and computer program product for coupled noise timing violation avoidance in detailed routing of an integrated circuit design are provided. The method includes calculating a noise induced timing violation sensitivity (NITVS) metric for nets in the integrated circuit design as a measure of sensitivity to a timing violation relative to a coupled noise delay adder, prioritizing routing isolation as a function of the NITVS metric for each of the nets to avoid coupled noise timing violations, and outputting the routing isolation priority.

Abstract: A routing method for reducing coupling between wires of an electronic circuit is proposed, wherein sets of nets are classified according to their coupling characteristics, and spacing between wires assigned to the sets of nets is chosen according to the coupling characteristics.

Abstract: A method for performing timing optimization of a detail routed netlist, incorporating statistical variability information, common path pessimism reduction, and capacitative coupling information, in a tightly coupled, incremental manner with minimal perturbations to the placement, routing, and asserted parasitic information. The method corrects violations in a placed and routed design of a VLSI circuit chip, where the design is represented by a netlist describing logical and physical characteristics of the design and by a corresponding timing graph, the method including the steps of: identifying violations in the design; iteratively eliminating the violations by incrementally transforming the logical and the physical characteristics of the design, incorporating in the design only legal placements and routes; and applying incremental timing to evaluate the transformations, and updating the existing timing graphs to reflect changes consisting of the legal placements and routes.

Abstract: A method, system, and computer program product for coupled noise timing violation avoidance in detailed routing of an integrated circuit design are provided. The method includes calculating a noise induced timing violation sensitivity (NITVS) metric for nets in the integrated circuit design as a measure of sensitivity to a timing violation relative to a coupled noise delay adder, prioritizing routing isolation as a function of the NITVS metric for each of the nets to avoid coupled noise timing violations, and outputting the routing isolation priority.

Abstract: A method for performing timing optimization of a detail routed netlist, incorporating statistical variability information, common path pessimism reduction, and capacitative coupling information, in a tightly coupled, incremental manner with minimal perturbations to the placement, routing, and asserted parasitic information. The method corrects violations in a placed and routed design of a VLSI circuit chip, where the design is represented by a netlist describing logical and physical characteristics of the design and by a corresponding timing graph, the method including the steps of: identifying violations in the design; iteratively eliminating the violations by incrementally transforming the logical and the physical characteristics of the design, incorporating in the design only legal placements and routes; and applying incremental timing to evaluate the transformations, and updating the existing timing graphs to reflect changes consisting of the legal placements and routes.

Abstract: A design structure for reducing coupling between wires of an electronic circuit is proposed, wherein sets of nets are classified according to their coupling characteristics, and spacing between wires assigned to the sets of nets is chosen according to the coupling characteristics.

Abstract: A routing method for reducing coupling between wires of an electronic circuit is proposed, wherein sets of nets are classified according to their coupling characteristics, and spacing between wires assigned to the sets of nets is chosen according to the coupling characteristics.

Abstract: A system and method for correcting wiring congestion in a placed and partially or fully globally-routed VLSI chip design while avoiding adding new timing or electrical violations or other design constraints. Globally-congested areas are identified along with determining terminated and non-terminated wires in the congested areas. The process includes optimizing the identified congestion areas, incrementally rerouting affected nets, testing the resultant design legality and congestion metrics, and committing or reversing the optimizations and reroutings. The optimizations further includes the movement of logic cells and decomposition, recomposition or any other modification of logic cell structures (possibly combined with cell movement) to move terminated wires to less congested grid edges, rearrangement of commutative connections within or between cells, or addition of buffers to cause reroutes of feedthrough wires.