Patents by Inventor Adam Pranda

Adam Pranda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12666892
    Abstract: A method for forming a semiconductor device can include providing a substrate having a patterned structure comprising semiconductor materials, where the patterned structure has a side profile including indentations, such as a patterned film stack, and where a spacer layer is conformally deposited over the patterned structure and within the indentations, reacting a surface of the spacer layer with a plasma-excited first etch gas to form a reacted layer on the spacer layer, wherein the plasma-excited first etch gas includes fluorine, hydrogen, and nitrogen, and removing at least part of the reacted layer by ion bombardment from exposure to a plasma-excited second etch gas. The spacer layer can be SiOCN. The reacted layer can be ammonium fluorosilicate. The first etch gas can contain SF6, H2, and N2, or NF3, H2, and N2. The reacting and removing can be done at room temperature in a same chamber.
    Type: Grant
    Filed: March 28, 2024
    Date of Patent: June 23, 2026
    Assignee: Tokyo Electron Limited
    Inventors: Adam Pranda, Christopher Catano, Yusuke Lent-Yoshida, Aelan Mosden, Yun Han, Ken Kobayashi
  • Publication number: 20260150600
    Abstract: A method includes forming a first layer over a substrate, patterning the first layer to form a plurality of recesses therein, forming a second layer on a top surface of the first layer and on sidewalls and bottoms of the recesses, selectively forming a protection layer on the bottoms of the recesses. Selectively forming the protection layer includes heating bottoms of the recesses with polarized light and depositing a material of the protection layer on the bottoms of the recesses. The method further includes performing a lateral etch process to reduce a thickness of the second layer at the sidewalls of the recesses.
    Type: Application
    Filed: November 25, 2024
    Publication date: May 28, 2026
    Inventors: David Eitan Barlaz, Adam Pranda
  • Patent number: 12575353
    Abstract: A method of processing a substrate that includes: forming a bottom passivation layer including an oxide over a first portion of a dielectric layer at a bottom of a recess of the substrate, the recess having sidewalls including a second portion of the dielectric layer; and performing a lateral etch to etch the second portion of the dielectric layer, the bottom passivation layer covering the first portion of the dielectric layer during the lateral etch, and where the forming of the bottom passivation layer includes exposing the substrate to a first plasma including a halogen, and exposing the substrate to a second plasma including oxygen to form the bottom passivation layer.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: March 10, 2026
    Assignee: Tokyo Electron Limited
    Inventors: Adam Pranda, Yusuke Yoshida, Aelan Mosden, Yun Han
  • Publication number: 20250246437
    Abstract: A method includes providing a workpiece in an etching apparatus at ambient temperature, the workpiece comprising a dielectric layer adjacent a conductive layer over a semiconductor substrate. The method includes performing an etching process to selectively remove the dielectric layer relative to the conductive layer. The method further includes, while performing the etching process, cooling the workpiece to a processing temperature that is below the ambient temperature.
    Type: Application
    Filed: January 26, 2024
    Publication date: July 31, 2025
    Applicant: Tokyo Electron Limited
    Inventors: Adam PRANDA, Yusuke YOSHIDA, Yun HAN
  • Publication number: 20250046617
    Abstract: A method of processing a substrate that includes: forming a bottom passivation layer including an oxide over a first portion of a dielectric layer at a bottom of a recess of the substrate, the recess having sidewalls including a second portion of the dielectric layer; and performing a lateral etch to etch the second portion of the dielectric layer, the bottom passivation layer covering the first portion of the dielectric layer during the lateral etch, and where the forming of the bottom passivation layer includes exposing the substrate to a first plasma including a halogen, and exposing the substrate to a second plasma including oxygen to form the bottom passivation layer.
    Type: Application
    Filed: July 31, 2023
    Publication date: February 6, 2025
    Inventors: Adam Pranda, Yusuke Yoshida, Aelan Mosden, Yun Han
  • Publication number: 20240379372
    Abstract: A method for forming a semiconductor device can include providing a substrate having a patterned structure comprising semiconductor materials, where the patterned structure has a side profile including indentations, such as a patterned film stack, and where a spacer layer is conformally deposited over the patterned structure and within the indentations, reacting a surface of the spacer layer with a plasma-excited first etch gas to form a reacted layer on the spacer layer, wherein the plasma-excited first etch gas includes fluorine, hydrogen, and nitrogen, and removing at least part of the reacted layer by ion bombardment from exposure to a plasma-excited second etch gas. The spacer layer can be SiOCN. The reacted layer can be ammonium fluorosilicate. The first etch gas can contain SF6, H2, and N2, or NF3, H2, and N2. The reacting and removing can be done at room temperature in a same chamber.
    Type: Application
    Filed: March 28, 2024
    Publication date: November 14, 2024
    Inventors: Adam Pranda, Christopher Catano, Yusuke Lent-Yoshida, Aelan Mosden, Yun Han, Ken Kobayashi