Abstract: A data processing system to implement wiring/silicon blockages via parameterized cells (pCells) includes a front end-of-line placement/blockage (FEOL P/B) controller to generate a placement blockage based on an input parameter corresponding to a physical design of an integrated circuit (IC). The FEOL P/B outputs a placement blockage parameter that is stored in a wire track allocation database to indicate the placement blockage. A back end-of-line wiring track (BEOL WT) controller generates a wire track blockage of the IC. A BEOL power track (BEOL PT) controller generates a metal blockage within the wire track blockage. A combination of the metal blockage and the wire track blockage defines a parent-child contract to enable concurrent physical design of the IC without creating shorts and overlaps in a child block of the IC.

Abstract: A data processing system to implement wiring/silicon blockages via parameterized cells (pCells) includes a front end-of-line placement/blockage (FEOL P/B) controller to generate a placement blockage based on an input parameter corresponding to a physical design of an integrated circuit (IC). The FEOL P/B outputs a placement blockage parameter that is stored in a wire track allocation database to indicate the placement blockage. A back end-of-line wiring track (BEOL WT) controller generates a wire track blockage of the IC. A BEOL power track (BEOL PT) controller generates a metal blockage within the wire track blockage. A combination of the metal blockage and the wire track blockage defines a parent-child contract to enable concurrent physical design of the IC without creating shorts and overlaps in a child block of the IC.

Abstract: A computer-implemented method of performing physical synthesis in a chip design process using hierarchical wire-pin co-optimization, a system, and a computer program product are described. Aspects include providing an indication of candidate pins among a plurality of pins of a plurality of macros that may be moved, and providing constraints on a range of movement of one or more of the plurality of pins. Aspects also include performing macro-level physical synthesis at each of the plurality of macros based on the candidate pins and the constraints to generate pin locations and timing results.

Abstract: A computer-implemented method of performing physical synthesis in a chip design process using hierarchical wire-pin co-optimization, a system, and a computer program product are described. Aspects include providing an indication of candidate pins among a plurality of pins of a plurality of macros that may be moved, and providing constraints on a range of movement of one or more of the plurality of pins. Aspects also include performing macro-level physical synthesis at each of the plurality of macros based on the candidate pins and the constraints to generate pin locations and timing results.

Abstract: Buffers are placed on selected nets coupled to input and output pins of entities in an IC device. This includes loading selected input and output pins of entities prior to respectively buffering nets of the entities and buffering in successive iterations, which includes setting artificial loads on selected input pins. The buffering in a current iteration is limited to i) buffering nets on the current iteration entity for receivers on the current iteration entity and ii) buffering nets on the current iteration entity directly coupled to respective nets of an immediately adjacent entity that has been buffered already in a preceding one of iterations, but only if the already buffered net is coupled to a receiver on its own net or a receiver on some other already buffered net via nets that have all been buffered via one or more of the preceding iterations.

Abstract: Buffers are placed on selected nets coupled to input and output pins of entities in an IC device. This includes loading selected input and output pins of entities prior to respectively buffering nets of the entities and buffering in successive iterations, which includes setting artificial loads on selected input pins. The buffering in a current iteration is limited to i) buffering nets on the current iteration entity for receivers on the current iteration entity and ii) buffering nets on the current iteration entity directly coupled to respective nets of an immediately adjacent entity that has been buffered already in a preceding one of iterations, but only if the already buffered net is coupled to a receiver on its own net or a receiver on some other already buffered net via nets that have all been buffered via one or more of the preceding iterations.

Abstract: A method, system, and computer program product for hierarchical integrated circuit repartitioning are provided. The method includes receiving parent level placement data for one or more interconnecting elements and designating at least one child to receive a pushdown of the one or more interconnecting elements from the parent level. For each child designated to receive the pushdown of the one or more interconnecting elements, the method further includes determining a physical coverage area of the child, identifying which of the one or more interconnecting elements within the physical coverage area of the child to pushdown into the child, generating an interconnecting element pushdown list for the child, including wiring layer information, and outputting the interconnecting element pushdown list.

Abstract: A method, system, and computer program product for hierarchical integrated circuit repartitioning are provided. The method includes receiving parent level placement data for one or more interconnecting elements and designating at least one child to receive a pushdown of the one or more interconnecting elements from the parent level. For each child designated to receive the pushdown of the one or more interconnecting elements, the method further includes determining a physical coverage area of the child, identifying which of the one or more interconnecting elements within the physical coverage area of the child to pushdown into the child, generating an interconnecting element pushdown list for the child, including wiring layer information, and outputting the interconnecting element pushdown list.

Abstract: A method (and a system for using the method) for automating a slew rate analysis between two or more circuits on a semiconductor chip. The method includes the steps of: receiving as input one or more input parameters characterizing the physical medium through which the signal propagation occurs (the net) and the electrical characteristics of signals transmitted between the circuits; and providing as output one or more output parameters characterizing the appropriate solution for physical implementation of the circuit(s) and net(s) which satisfy the performance requirements of the system. The receiving step can comprise any one of: providing a hierarchical signal name cross-reference defining a name for the signal for a given hierarchy level of the circuits; providing a set of one or more boolean equations used to generate the one or more output parameters from the one or more input parameters; providing a physical design information for the circuits; and providing a timing information for the signals.