Abstract: Systems and methods for improving the efficiency of a rotational dynamic element matching (DEM) for Delta Sigma converters. In some implementations, the systems and methods are provided for reducing intersymbol interference (ISI) of a Delta Sigma converter. A delta sigma converter architecture can include multiple I-DACs, and the output from each I-DAC can vary from the other l-DACs. Techniques include decreasing mismatch among multiple l-DACs while improving efficiency of rotational dynamic element matching.

Abstract: Systems and methods for improving noise efficiency in a Delta Sigma modulator. A bypass scheme for a noise splitter is disclosed that reduces toggling activity for small signals. In particular, a sample-by-sample bypass noise splitter is disclosed that includes a noise splitting module and a bypass line. The bypass line bypasses the noise splitting module when signals are below a selected threshold, increasing efficiency of the system.

Abstract: Sensor apparatus and methods for operating the same for measuring acceleration are disclosed. In some embodiments, circuitry inside a sensor digitizes a measured acceleration signal from an accelerometer into a digitized acceleration signal, which is processed by a digital equalization filter within the sensor to provide an equalized acceleration signal. The equalized acceleration signal may have a frequency response that is substantially flat over a frequency range that extends beyond the resonant frequency of a MEMs sensor within the accelerometer of the sensor.

Abstract: Systems and methods for a power-efficient 3-level digital-to-analog converter. A converter cell using a current starving technique keeps a portion of the converter cell turned on in a low power mode, as opposed to completely turning off current in selected modes. A conversion system keeps a first set of converters active while allowing a second set of converters to be powered down. Systems and methods presented save power and allow for efficient reactivation of converters.

Abstract: Systems and method for improving stability and performance in class-D modulators. In particular, a multi-cycle feedback network is positioned around a quantizer of a digital class-D amplifier. The multi-cycle feedback network allows the main class-D feedback loop to have multiple clock cycles of delay.

Abstract: Systems and methods for improving the efficiency of a rotational dynamic element matching (DEM) for Delta Sigma converters. In some implementations, the systems and methods are provided a for reducing intersymbol interference (ISI) of a Delta Sigma converter. A delta sigma converter architecture can include multiple I-DACs, and the output from each I-DAC can vary from the other I-DACs. Techniques are disclosed for decreasing mismatch among multiple I-DACs while improving efficiency of rotational dynamic element matching.

Abstract: Systems and methods for a power-efficient 3-level digital-to-analog converter. A converter cell using a current starving technique keeps a portion of the converter cell turned on in a low power mode, as opposed to completely turning off current in selected modes. A conversion system keeps a first set of converters active while allowing a second set of converters to be powered down. Systems and methods presented save power and allow for efficient reactivation of converters.

Abstract: Systems and methods for improving noise efficiency in a Delta Sigma modulator. A bypass scheme for a noise splitter is disclosed that reduces toggling activity for small signals. In particular, a sample-by-sample bypass noise splitter is disclosed that includes a noise splitting module and a bypass line. The bypass line bypasses the noise splitting module when signals are below a selected threshold, increasing efficiency of the system.

Abstract: Sensor apparatus and methods for operating the same for measuring acceleration are disclosed. In some embodiments, circuitry inside a sensor digitizes a measured acceleration signal from an accelerometer into a digitized acceleration signal, which is processed by a digital equalization filter within the sensor to provide an equalized acceleration signal. The equalized acceleration signal may have a frequency response that is substantially flat over a frequency range that extends beyond the resonant frequency of a MEMs sensor within the accelerometer of the sensor.

Abstract: There is disclosed in one example a digital phase-locked loop (DPLL) circuit adapted to avoid loop-bandwidth tradeoff, the circuit including: a frequency dimension frequency detector having an external frequency input and a feedback frequency input, the frequency dimension frequency detector including circuitry to measure a frequency difference between the external frequency input and the feedback frequency input and to drive an impulse signal, wherein the impulse signal is of a first species if the difference is positive and of a second species if the difference is negative; and a number-controlled oscillator (NCO) including circuitry to drive an output clock and to adjust the frequency of the output clock responsive to the impulse signal, wherein an output of the NCO provides the feedback frequency input of the frequency dimension frequency detector.

Abstract: There is disclosed in one example a digital phase-locked loop (DPLL) circuit adapted to avoid loop-bandwidth tradeoff, the circuit including: a frequency dimension frequency detector having an external frequency input and a feedback frequency input, the frequency dimension frequency detector including circuitry to measure a frequency difference between the external frequency input and the feedback frequency input and to drive an impulse signal, wherein the impulse signal is of a first species if the difference is positive and of a second species if the difference is negative; and a number-controlled oscillator (NCO) including circuitry to drive an output clock and to adjust the frequency of the output clock responsive to the impulse signal, wherein an output of the NCO provides the feedback frequency input of the frequency dimension frequency detector.

Abstract: There is disclosed in one example a digital phase-locked loop (DPLL) circuit adapted to avoid loop-bandwidth tradeoff, the circuit including: a frequency dimension frequency detector having an external frequency input and a feedback frequency input, the frequency dimension frequency detector including circuitry to measure a frequency difference between the external frequency input and the feedback frequency input and to drive an impulse signal, wherein the impulse signal is of a first species if the difference is positive and of a second species if the difference is negative; and a number-controlled oscillator (NCO) including circuitry to drive an output clock and to adjust the frequency of the output clock responsive to the impulse signal, wherein an output of the NCO provides the feedback frequency input of the frequency dimension frequency detector.

Abstract: There is disclosed in one example a digital phase-locked loop (DPLL) circuit adapted to avoid loop-bandwidth tradeoff, the circuit including: a frequency dimension frequency detector having an external frequency input and a feedback frequency input, the frequency dimension frequency detector including circuitry to measure a frequency difference between the external frequency input and the feedback frequency input and to drive an impulse signal, wherein the impulse signal is of a first species if the difference is positive and of a second species if the difference is negative; and a number-controlled oscillator (NCO) including circuitry to drive an output clock and to adjust the frequency of the output clock responsive to the impulse signal, wherein an output of the NCO provides the feedback frequency input of the frequency dimension frequency detector.

Abstract: In a cascaded integrator comb (CIC) filter, a time-varying gain is added before the last integrating stage transforming its sub optimal boxcar impulse response into an FIR filter of arbitrary length. Make the coefficients sparse and taking them from a set of small integers leads to an efficient hardware implementation that does not compromise any of the essential CIC filter characteristics especially the overflow handling. The proposed sparse CIC structure can improve the worst case stop band attenuation by as much as 10 dB while occupying 77% of the chip area and consuming 30% less power compared to a standard a 5th order CIC filter, and reducing the overall bit growth of the filter and the amount of high rate operations. Design examples are given illustrating the advantages and flexibility of the proposed structure.

Abstract: In a cascaded integrator comb (CIC) filter, a time-varying gain is added before the last integrating stage transforming its sub optimal boxcar impulse response into an FIR filter of arbitrary length. Make the coefficients sparse and taking them from a set of small integers leads to an efficient hardware implementation that does not compromise any of the essential CIC filter characteristics especially the overflow handling. The proposed sparse CIC structure can improve the worst case stop band attenuation by as much as 10 dB while occupying 77% of the chip area and consuming 30% less power compared to a standard a 5th order CIC filter, and reducing the overall bit growth of the filter and the amount of high rate operations. Design examples are given illustrating the advantages and flexibility of the proposed structure.