Abstract: In an integrated circuit (IC) analysis, a reference IC layout is stored. Instructions are readable and executable by an electronic processor to perform an IC analysis method, including: receiving layer images of a physical IC; extracting polygons depicted in the layer images; detecting errors in the physical IC by applying homeomorphic error detection to compare the extracted polygons with polygons of the reference IC layout; and displaying the detected errors on the display. The detecting of errors may include detecting an error comprising a topological inequivalence between an extracted polygon or pair of polygons and a polygon or pair of polygons of the reference IC layout. The detecting of errors may include detecting an error comprising a topological coverage error.

Abstract: An integrated circuit (IC) layout extraction method includes executing: an image receiving pipeline that, for each tile n of N tiles of an IC, receives a tile image n of the tile n of the IC acquired using a microscope; a layout portion extraction pipeline that extracts a layout portion n from each received tile image n; and a layout portion comparison pipeline that compares each layout portion n with a corresponding portion of the reference IC layout. The image receiving pipeline, the layout portion extraction pipeline, and the layout portion comparison pipeline are parallel pipelines that are executed by the electronic processor concurrently in time. The extracted layout portions for the N tiles of the IC are combined to form the extracted layout for the IC.