Patents by Inventor Adam Rak

Adam Rak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system for mapping an integral into a thread of a parallel architecture
    Patent number: 10102043
    Abstract: A method is disclosed for mapping an integral into a thread of a parallel architecture, in the course of which the integral is mapped into a summation expressed by coefficient values and summation values, and a directed graph is generated corresponding to the computation of the summation. Furthermore, in the course of the method a level of a traversal sequence to each of the nodes is assigned, respectively, and at each level of the traversal sequence, a storage location of the intermediate value corresponding to the edge connected with its input to the node corresponding to the given level is specified in a memory corresponding to the thread and including a register storage, a local storage, and a global storage. A system is also disclosed for mapping an integral into a thread of a parallel architecture.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: October 16, 2018
    Assignees: Furukawa Electric Technologies Intezet Kft., Pazmany Peter Katolikus Egyetem, StreamNovation Kft.
    Inventors: Adam Rak, Gergely Feldhoffer, Gergely Balazs Soos, Tibor Holtzl, Balazs Oroszi, Gyorgy Gabor Cserey
  • Method And System For Mapping An Integral Into A Thread Of A Parallel Architecture
    Publication number: 20150128151
    Abstract: A method is disclosed for mapping an integral into a thread of a parallel architecture, in the course of which the integral is mapped into a summation expressed by coefficient values and summation values, and a directed graph is generated corresponding to the computation of the summation. Furthermore, in the course of the method a level of a traversal sequence to each of the nodes is assigned, respectively, and at each level off the traversal sequence, a storage location of the intermediate value corresponding to the edge connected with its input to the node corresponding to the given level is specified in a memory corresponding to the thread and including a register storage, a local storage, and a global storage. A system is also disclosed for mapping an integral into a thread of a parallel architecture.
    Type: Application
    Filed: May 31, 2013
    Publication date: May 7, 2015
    Applicant: StreamNovation Kft.
    Inventors: Adam Rak, Gergely Feldhoffer, Gergely Balazs Soos, Tibor Holtzl, Balazs Oroszi, Gyorgy Gabor Cserey