Abstract: An apparatus is provided comprising rewritable storage circuitry to store at least one mapping between at least one instruction identifier and a behaviour modification. Selection circuitry selects, from the rewritable storage circuitry, a selected mapping having an instruction identifier that identifies a received instruction. The received instruction causes a data processing unit to perform a default behaviour. Control circuitry causes the data processing unit to behave in accordance with the default behaviour modified by the behaviour modification.

Abstract: An apparatus is provided comprising rewritable storage circuitry to store at least one mapping between at least one instruction identifier and a behaviour modification. Selection circuitry selects, from the rewritable storage circuitry, a selected mapping having an instruction identifier that identifies a received instruction. The received instruction causes a data processing unit to perform a default behaviour. Control circuitry causes the data processing unit to behave in accordance with the default behaviour modified by the behaviour modification.

Abstract: An apparatus has decoding circuitry to decode instructions to generate micro-operations, and register rename circuitry to map architectural register specifiers specified by the instructions to physical registers to be accessed in response to the micro-operations. In response to an instruction specifying a selected architectural register specifier as both a source register and a destination register, for which the decoding circuitry is to generate two or more micro-operations, the register rename circuitry stores an indication of a physical register previously mapped to said selected architectural register specifier.