Abstract: A DC power supply may use an input supply surge protection circuit that may be robust against positive and negative power surges. DC power may be provided through a first unidirectional circuit component such as a diode or selectively controlled MOSFET coupled in parallel with a transient voltage suppressor or Zener diode. The first unidirectional circuit component may have a first voltage rating and the transient voltage suppressor or Zener diode may have a second voltage rating lower than the first voltage rating. This may allow current to flow backward over the transient voltage suppressor or Zener diode to protect the first unidirectional circuit component from exposure to voltage beyond the first voltage rating in a power surge.

Abstract: Methods, systems, and devices for ferroelectric memory plate power reduction are described. A plate line may be coupled with a voltage source, a capacitor, and one or more sections of a bank of ferroelectric memory cells. During a write operation, the capacitor may be discharged onto the plate line and the resulting voltage may be adjusted (e.g., increased) by the voltage source before writing one or more memory cells. During a write-back operation, a capacitor associated with one or more memory cells may be discharged onto the plate line and stored at the capacitor. The charge may be re-applied to the plate line and adjusted (e.g., increased) by the voltage source during the write-back.

Abstract: Devices and methods for sensing a memory cell are described. The memory cell may include a ferroelectric memory cell. During a read operation, a first switching component may selectively couple a sense component with the memory cell based on a logic state stored on the memory cell to transfer a charge between the memory cell and the sense component. A second switching component, which may be coupled with the first switching component, may down convert a voltage associated with the charge to another voltage that is within an operation voltage of the sense component. The sense component may operate at a lower voltage than a voltage at which the memory cell operates to reduce power consumption in some cases.

Abstract: A DC power supply may use an input supply surge protection circuit that may be robust against positive and negative power surges. DC power may be provided through a first unidirectional circuit component such as a diode or selectively controlled MOSFET coupled in parallel with a transient voltage suppressor or Zener diode. The first unidirectional circuit component may have a first voltage rating and the transient voltage suppressor or Zener diode may have a second voltage rating lower than the first voltage rating. This may allow current to flow backward over the transient voltage suppressor or Zener diode to protect the first unidirectional circuit component from exposure to voltage beyond the first voltage rating in a power surge.

Abstract: Methods, systems, and devices for an arbitrated sense amplifier are described. A memory device may couple a memory cell to a first node via a digit line and may couple the first node to a second node. If a voltage at the second node is associated with a first logic value stored at the memory cell, the memory device may couple the second node with a third node and may charge the third node according to the voltage. However, if the voltage at the second node is associated with a second logic value stored at the memory cell, the memory device may not couple the second node with the third node. The memory device may compare the resulting voltage at the third node with a reference voltage and may generate a signal indicative of a logic value stored by the memory cell.

Abstract: Methods, systems, and devices for an arbitrated sense amplifier are described. A memory device may couple a memory cell to a first node via a digit line and may couple the first node to a second node. If a voltage at the second node is associated with a first logic value stored at the memory cell, the memory device may couple the second node with a third node and may charge the third node according to the voltage. However, if the voltage at the second node is associated with a second logic value stored at the memory cell, the memory device may not couple the second node with the third node. The memory device may compare the resulting voltage at the third node with a reference voltage and may generate a signal indicative of a logic value stored by the memory cell.

Abstract: Devices and methods for sensing a memory cell are described. The memory cell may include a ferroelectric memory cell. During a read operation, a first switching component may selectively couple a sense component with the memory cell based on a logic state stored on the memory cell to transfer a charge between the memory cell and the sense component. A second switching component, which may be coupled with the first switching component, may down convert a voltage associated with the charge to another voltage that is within an operation voltage of the sense component. The sense component may operate at a lower voltage than a voltage at which the memory cell operates to reduce power consumption in some cases.

Abstract: Methods, systems, and devices for ferroelectric memory plate power reduction are described. A plate line may be coupled with a voltage source, a capacitor, and one or more sections of a bank of ferroelectric memory cells. During a write operation, the capacitor may be discharged onto the plate line and the resulting voltage may be adjusted (e.g., increased) by the voltage source before writing one or more memory cells. During a write-back operation, a capacitor associated with one or more memory cells may be discharged onto the plate line and stored at the capacitor. The charge may be re-applied to the plate line and adjusted (e.g., increased) by the voltage source during the write-back.

Abstract: Methods and devices for reading a memory cell using multi-stage memory sensing are described. The memory cell may be coupled to a digit line after the digit line during a read operation. A transistor may be activated to couple an amplifier capacitor with the digit line during the read operation. The transistor may be deactivated for a portion of the read operation to isolate the amplifier capacitor from the digit line while the memory cell is coupled to the digit line. The transistor may be reactivated to recouple the amplifier capacitor to the digit line to help determine the value of the memory cell.

Abstract: Devices and methods for sensing a memory cell are described. The memory cell may include a ferroelectric memory cell. During a read operation, a first switching component may selectively couple a sense component with the memory cell based on a logic state stored on the memory cell to transfer a charge between the memory cell and the sense component. A second switching component, which may be coupled with the first switching component, may down convert a voltage associated with the charge to another voltage that is within an operation voltage of the sense component. The sense component may operate at a lower voltage than a voltage at which the memory cell operates to reduce power consumption in some cases.

Abstract: Methods and devices for reading a memory cell using multi-stage memory sensing are described. The memory cell may be coupled to a digit line after the digit line during a read operation. A transistor may be activated to couple an amplifier capacitor with the digit line during the read operation. The transistor may be deactivated for a portion of the read operation to isolate the amplifier capacitor from the digit line while the memory cell is coupled to the digit line. The transistor may be reactivated to recouple the amplifier capacitor to the digit line to help determine the value of the memory cell.

Abstract: Methods, systems, and devices for cell voltage accumulation discharge are described. One or more sections of a bank of ferroelectric memory cells may be coupled with one or more access lines. By activating one or more switching components, one or more sections (that may include a memory array and/or a driver) of memory cells may be isolated. When isolated, a voltage may be applied across an access line associated with the section to activate an access device of each memory cell. By activating a switching component of a respective memory cell, a capacitor of the memory cell may be discharged and then the isolated section may be coupled with the plurality of access lines.

Abstract: Methods, systems, and devices for an arbitrated sense amplifier are described. A memory device may couple a memory cell to a first node via a digit line and may couple the first node to a second node. If a voltage at the second node is associated with a first logic value stored at the memory cell, the memory device may couple the second node with a third node and may charge the third node according to the voltage. However, if the voltage at the second node is associated with a second logic value stored at the memory cell, the memory device may not couple the second node with the third node. The memory device may compare the resulting voltage at the third node with a reference voltage and may generate a signal indicative of a logic value stored by the memory cell.

Abstract: Methods, systems, and devices for ferroelectric memory plate power reduction are described. A plate line may be coupled with a voltage source, a capacitor, and one or more sections of a bank of ferroelectric memory cells. During a write operation, the capacitor may be discharged onto the plate line and the resulting voltage may be adjusted (e.g., increased) by the voltage source before writing one or more memory cells. During a write-back operation, a capacitor associated with one or more memory cells may be discharged onto the plate line and stored at the capacitor. The charge may be re-applied to the plate line and adjusted (e.g., increased) by the voltage source during the write-back.

Abstract: Methods and devices for reading a memory cell using multi-stage memory sensing are described. The memory cell may be coupled to a digit line after the digit line during a read operation. A transistor may be activated to couple an amplifier capacitor with the digit line during the read operation. The transistor may be deactivated for a portion of the read operation to isolate the amplifier capacitor from the digit line while the memory cell is coupled to the digit line. The transistor may be reactivated to recouple the amplifier capacitor to the digit line to help determine the value of the memory cell.

Abstract: Methods and devices for reading a memory cell using multi-stage memory sensing are described. The memory cell may be coupled to a digit line after the digit line during a read operation. A transistor may be activated to couple an amplifier capacitor with the digit line during the read operation. The transistor may be deactivated for a portion of the read operation to isolate the amplifier capacitor from the digit line while the memory cell is coupled to the digit line. The transistor may be reactivated to recouple the amplifier capacitor to the digit line to help determine the value of the memory cell.

Abstract: Apparatuses for supplying power supply voltage in a plurality of dies are described. An example apparatus includes: a circuit board; a regulator on the circuit board that regulates a first voltage; a semiconductor device on the circuit board that receives the first voltage through a power line in the circuit board. The semiconductor device includes: a substrate on the circuit board, stacked via conductive balls, that receives the first voltage from the power line via the conductive balls; a plurality of dies on the semiconductor device, stacked via bumps, each die including, a first conductive via that receives the first voltage via the bumps; a plurality of pillars between adjacent dies and couple the first conductive vias of the adjacent dies; and a sense node switch circuit that selectively couples one first conductive via of one die among the plurality of dies to the regulator.

Abstract: Methods, systems, and devices for cell voltage accumulation discharge are described. One or more sections of a bank of ferroelectric memory cells may be coupled with one or more access lines. By activating one or more switching components, one or more sections (that may include a memory array and/or a driver) of memory cells may be isolated. When isolated, a voltage may be applied across an access line associated with the section to activate an access device of each memory cell. By activating a switching component of a respective memory cell, a capacitor of the memory cell may be discharged and then the isolated section may be coupled with the plurality of access lines.

Abstract: Methods, systems, and devices for ferroelectric memory plate power reduction are described. A plate line may be coupled with a voltage source, a capacitor, and one or more sections of a bank of ferroelectric memory cells. During a write operation, the capacitor may be discharged onto the plate line and the resulting voltage may be adjusted (e.g., increased) by the voltage source before writing one or more memory cells. During a write-back operation, a capacitor associated with one or more memory cells may be discharged onto the plate line and stored at the capacitor. The charge may be re-applied to the plate line and adjusted (e.g., increased) by the voltage source during the write-back.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for plate coupled sense amplifiers. An example embodiment may include a sense amplifier which may sense a voltage from a memory cell. The sense amplifier may also monitor a change in the voltage, and determine a logical value of the memory cell based on the time when the voltage reaches a trigger voltage. The memory cell may be coupled to a plate with a plate voltage, wherein a change in the plate voltage determines the change of the voltage from the memory cell.