Patents by Inventor Adam Selsley

Adam Selsley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9502232
    Abstract: Methods for fabricating a layered circuit structure are provided, which include, for instance: depositing a first material layer above a substrate, the first material layer having an oxidized upper surface; providing a second material layer over the oxidized upper surface of the first material layer; and inhibiting diffusion of one or more elements from the oxidized upper surface of the first material layer into either the first material layer or the second material layer during the providing of the second material layer over the oxidized upper surface of the first material layer. The inhibiting may include one or more of modifying a characteristic(s) of the first material layer, forming a protective layer over the oxidized upper surface of the first material layer, or altering at least one process parameter employed in providing the second material layer.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: November 22, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sipeng Gu, Sandeep Gaan, Zhiguo Sun, Huang Liu, Adam Selsley
  • Publication number: 20160005598
    Abstract: Methods for fabricating a layered circuit structure are provided, which include, for instance: depositing a first material layer above a substrate, the first material layer having an oxidized upper surface; providing a second material layer over the oxidized upper surface of the first material layer; and inhibiting diffusion of one or more elements from the oxidized upper surface of the first material layer into either the first material layer or the second material layer during the providing of the second material layer over the oxidized upper surface of the first material layer. The inhibiting may include one or more of modifying a characteristic(s) of the first material layer, forming a protective layer over the oxidized upper surface of the first material layer, or altering at least one process parameter employed in providing the second material layer.
    Type: Application
    Filed: July 2, 2014
    Publication date: January 7, 2016
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Sipeng GU, Sandeep GAAN, Zhiguo SUN, Huang LIU, Adam SELSLEY
  • Publication number: 20120220091
    Abstract: A method for forming thick oxide at the bottom of a trench formed in a semiconductor substrate includes forming a conformal oxide film by a sub-atmospheric chemical vapor deposition process that fills the trench and covers a top surface of the substrate. The method also includes etching the oxide film off the top surface of the substrate and inside the trench to leave a substantially flat layer of oxide having a target thickness at the bottom of the trench.
    Type: Application
    Filed: March 12, 2012
    Publication date: August 30, 2012
    Inventors: Ashok Challa, Alan Elbanhawy, Thomas E. Grebs, Nathan L. Kraft, Dean E. Probst, Rodney S. Ridley, Steven P. Sapp, Qi Wang, Chongman Yun, J.G. Lee, Peter H. Wilson, Joseph A. Yedinak, J.Y. Jung, H.C. Jang, Babak S. Sani, Richard Stokes, Gary M. Dolny, John Mytych, Becky Losee, Adam Selsley, Robert Herrick, James J. Murphy, Gordon K. Madson, Bruce D. Marchant, Christopher L. Rexer, Christopher B. Kocon, Debra S. Woolsey
  • Patent number: 8227344
    Abstract: According to one embodiment, the method includes providing a substrate containing a metal-containing barrier layer having an oxidized surface layer, exposing the oxidized surface layer to a flow of a first process gas containing plasma-excited argon gas to activate the oxidized surface layer and applying substrate bias power during the exposing of the oxidized surface layer to the flow of the first process gas. The method further includes exposing the activated oxidized surface layer to a second process gas containing non-plasma-excited hydrogen gas, wherein the exposure to the first process gas, in addition to activating the oxidized surface layer, facilitates chemical reduction of the activated oxidized surface layer by the second process gas containing the hydrogen gas. A thickness of the metal-containing barrier layer is not substantially changed by the hybrid in-situ dry cleaning process.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: July 24, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Adam Selsley, Frank M. Cerio, Jr.
  • Patent number: 8143123
    Abstract: A method for forming power semiconductor devices having an inter-electrode dielectric (IPD) layer inside a trench includes providing a semiconductor substrate with a trench, lining the sidewalls and bottom of the trench with a first layer of dielectric material, filling the trench with a first layer of conductive material to form a first electrode, recessing the first layer of dielectric material and the first layer of conductive material to a first depth inside the trench, forming a layer of polysilicon material on a top surface of the dielectric material and conductive material inside the trench, oxidizing the layer of polysilicon material, and forming a second electrode inside the trench atop the oxidized layer and isolated from trench sidewalls by a second dielectric layer. The oxidation step can be enhanced by either chemically or physically altering the top portion polysilicon such as by implanting impurities.
    Type: Grant
    Filed: March 3, 2008
    Date of Patent: March 27, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Thomas E. Grebs, Rodney S. Ridley, Steven P. Sapp, Peter H. Wilson, Babak S. Sani, Gary M. Dolny, John Mytych, Becky Losee, Adam Selsley, Christopher B. Kocon
  • Publication number: 20110212274
    Abstract: According to one embodiment, the method includes providing a substrate containing a metal-containing barrier layer having an oxidized surface layer, exposing the oxidized surface layer to a flow of a first process gas containing plasma-excited argon gas to activate the oxidized surface layer and applying substrate bias power during the exposing of the oxidized surface layer to the flow of the first process gas. The method further includes exposing the activated oxidized surface layer to a second process gas containing non-plasma-excited hydrogen gas, wherein the exposure to the first process gas, in addition to activating the oxidized surface layer, facilitates chemical reduction of the activated oxidized surface layer by the second process gas containing the hydrogen gas. A thickness of the metal-containing barrier layer is not substantially changed by the hybrid in-situ dry cleaning process.
    Type: Application
    Filed: February 26, 2010
    Publication date: September 1, 2011
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Adam Selsley, Frank M. Cerio, JR.
  • Publication number: 20080199997
    Abstract: A method for forming power semiconductor devices having an inter-electrode dielectric (IPD) layer inside a trench includes providing a semiconductor substrate with a trench, lining the sidewalls and bottom of the trench with a first layer of dielectric material, filling the trench with a first layer of conductive material to form a first electrode, recessing the first layer of dielectric material and the first layer of conductive material to a first depth inside the trench, forming a layer of polysilicon material on a top surface of the dielectric material and conductive material inside the trench, oxidizing the layer of polysilicon material, and forming a second electrode inside the trench atop the oxidized layer and isolated from trench sidewalls by a second dielectric layer. The oxidation step can be enhanced by either chemically or physically altering the top portion polysilicon such as by implanting impurities.
    Type: Application
    Filed: March 3, 2008
    Publication date: August 21, 2008
    Inventors: Thomas E. Grebs, Rodney S. Ridley, Steven P. Sapp, Peter H. Wilson, Babak S. Sani, Gary M. Dolny, John Mytych, Becky Losee, Adam Selsley, Christopher B. Kocon
  • Publication number: 20080150020
    Abstract: A semiconductor power device includes a drift region of a first conductivity type, a well region extending above the drift region and having a second conductivity type opposite the first conductivity type, an active trench extending through the well region and into the drift region. The active trench, which includes sidewalls and bottom lined with dielectric material, is substantially filled with a first conductive layer and a second conductive layer. The second conductive layer forms a gate electrode and is disposed above the first conductive layer and is separated from the first conductive layer by an inter-electrode dielectric material. The device also includes source regions having the first conductivity type formed inside the well region and adjacent the active trench and a charge control trench that extends deeper into the drift region than the active trench and is substantially filled with material to allow for vertical charge control in the drift region.
    Type: Application
    Filed: January 22, 2008
    Publication date: June 26, 2008
    Inventors: Ashok Challa, Alan Elbanhawy, Thomas E. Grebs, Nathan L. Kraft, Dean E. Probst, Rodney S. Ridley, Steven P. Sapp, Qi Wang, Chongman Yun, J. G. Lee, Peter H. Wilson, Joseph A. Yedinak, J. Y. Jung, H. C. Jang, Babak S. Sani, Richard Stokes, Gary M. Dolny, John Mytych, Becky Losee, Adam Selsley, Robert Herrick, James J. Murphy, Gordon K. Madson, Bruce D. Marchant, Christopher L. Rexer, Christopher B. Kocon, Debra S. Woolsey
  • Publication number: 20080135931
    Abstract: A semiconductor power device includes a drift region of a first conductivity type, a well region extending above the drift region and having a second conductivity type opposite the first conductivity type, an active trench extending through the well region and into the drift region, source regions having the first conductivity type formed in the well region adjacent the active trench, and a first termination trench extending below the well region and disposed at an outer edge of an active region of the device. The sidewalls and bottom of the active trench are lined with dielectric material, and substantially filled with a first conductive layer forming an upper electrode and a second conductive layer forming a lower electrode, the upper electrode being disposed above the lower electrode and separated therefrom by inter-electrode dielectric material.
    Type: Application
    Filed: February 15, 2008
    Publication date: June 12, 2008
    Inventors: Ashok Challa, Alan Elbanhawy, Thomas E. Grebs, Nathan L. Kraft, Dean E. Probst, Rodney S. Ridlay, Steven P. Sapp, Qi Wang, Chongman Yun, J.G. Lee, Peter H. Wilson, Joseph A. Yedinak, J.Y. Jung, H.C. Jang, Babak S. Sanl, Richard Stokes, Gary M. Dolny, John Mytych, Becky Losee, Adam Selsley, Robert Herrick, James J. Murphy, Gordon K. Madson, Bruce D. Marchant, Christopher L. Rexer, Christopher B. Kocon, Debra S. Woolsey
  • Publication number: 20060214221
    Abstract: Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented.
    Type: Application
    Filed: May 31, 2006
    Publication date: September 28, 2006
    Inventors: Ashok Challa, Alan Elbanhawy, Thomas Grebs, Nathan Kraft, Dean Probst, Rodney Ridley, Steven Sapp, Qi Wang, Chongman Yun, J.G. Lee, Peter Wilson, Joseph Yedinak, J.Y. Jung, H.C. Jang, Babak Sani, Richard Stokes, Gary Dolny, John Mytych, Becky Losee, Adam Selsley, Robert Herrick, James Murphy, Gordon Madson, Bruce Marchant, Christopher Rexer, Christopher Kocon, Debra Woolsey
  • Publication number: 20060214222
    Abstract: Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented.
    Type: Application
    Filed: May 31, 2006
    Publication date: September 28, 2006
    Inventors: Ashok Challa, Alan Elbanhawy, Thomas Grebs, Nathan Kraft, Dean Probst, Rodney Ridley, Steven Sapp, Qi Wang, Chongman Yun, J. Lee, Peter Wilson, Joseph Yedinak, J. Jung, H. Jang, Babak Sani, Richard Stokes, Gary Dolny, John Mytych, Becky Losee, Adam Selsley, Robert Herrick, James Murphy, Gordon Madson, Bruce Marchant, Christopher Rexer, Christopher Kocon, Debra Woolsey
  • Publication number: 20050167742
    Abstract: Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented.
    Type: Application
    Filed: December 29, 2004
    Publication date: August 4, 2005
    Applicant: Fairchild Semiconductor Corp.
    Inventors: Ashok Challa, Alan Elbanhawy, Thomas Grebs, Nathan Kraft, Dean Probst, Rodney Ridley, Steven Sapp, Qi Wang, Chongman Yun, J.G. Lee, Peter Wilson, Joseph Yedinak, J.Y. Jung, H.C. Jang, Babak Sani, Richard Stokes, Gary Dolny, John Mytych, Becky Losee, Adam Selsley, Robert Herrick, James Murphy, Gordon Madson, Bruce Marchant, Christopher Rexer, Christopher Kocon, Debra Woolsey