Abstract: Basic server resources may be extended by the completion of a Capacity on Demand (CoD) Agreement. The CoD Agreement provides authorization to the server for activation of inactive resources. A Power On Self Test (POST) works in conjunction with a system management interrupt, a memory unit, and a plurality of Peripheral Component Interconnect (PCI) host bridges to provide for on demand additions of input and output adapters. The adapters may be added during various phases of operation and may be hot pluggable.

Abstract: Methods and arrangements to dynamically modify the number of processors active in a multi-node data processing system. are contemplated. Embodiments include transformations, code, state machines or other logic to change the portion of BIOS that a processor loads on power-on. In some embodiments, a signal sent over a GPIO pin may flip an address line to the portion of the BIO that a processor loads on power-on. In some embodiments, a service processor may set a GPIO or non-volatile RAM value. The portion of BIOS controlling the powering-up of the processor may read the value and branch depending upon the value. Embodiments also include transformations, code, state machines or other logic to determine the state of a dynamically activated processor. In some embodiments, a processor may read from a local scratch register to determine if it has been dynamically activated. If so, embodiments may then clear the scratch register and put the processor to sleep.

Abstract: In a multi-node system, a node can be dynamically detached (e.g., responsive to an error situation) without impacting the operating system or others of the nodes. Contents of in-use memory at the node to be detached are copied to another node, and a memory map is updated to make the copy transparent to components using the memory. Furthermore, the copied-to memory locations are programmatically blocked to prevent assignment thereof to a memory requester.

Abstract: In a multi-node SMP system, at least one processor per node is enabled to execute the SMM task for the hardware resources that are local to that node. Additionally, each node is allocated its own local SMM code copy in its own SMM memory segment, to allow for improved access and a further reduction in internode traffic. In a preferred embodiment, only a signle processor per node is enabled to execute the SMM tasks, and specific SMM memory locations within the SMM memory segments are allocated and used to report status and results from each node. A root node SMM processor monitors the SMM status entries of the other nodes for completion. To further reduce run-time internode traffic, a per-node resource map is created to identify memory and I/O resources that are specific to a particular node. This per-node resource map is then stored locally within the SMM space on each node, respectively.

Abstract: A method and system for booting up multiple PCI peripheral devices, such that the number of bootable PCI peripheral devices is not limited by the amount of computer system memory that is dedicated to storing executable boot code for the peripheral devices. The executable boot code is stored on a Read Only Memory (ROM) on each peripheral device. When a new PCI peripheral device begins to boot up, a check for available memory space in a ROM scan memory address space is performed. If there is not enough available room in the ROM scan memory address space for the new device's executable boot code, then a ROM scan detection logic pages an image of another peripheral device's executable boot code out of the ROM scan memory address space before storing the new device's executable boot code into the ROM scan memory address space.

Abstract: A method and system for method of removing a node from a multi-node computer. The node receives a system management interrupt (SMI), resulting in a quiescenting of only that node. The SMI receiving node then polls other nodes in the multi-node computer to determine if the SMI affects an operation of any of the other nodes, and quiescents any other node affected by the SMI. Each quiescent node then transfers all of the contents of its system memory to a backup memory in an unaffected remote node in the multi-node computer. The remote node than assumes the function of the removed node that had received the SMI. The method and system thus allows node removal in the event of a hot-swap request or a predicted failure of a node.

Abstract: A method, system, and program product supporting dynamic configuring of a multi-node computer. The system includes a scalability management module directly coupled to each node in the multi-node computer.

Abstract: A method and system for method of removing a node from a multi-node computer. The node receives a system management interrupt (SMI), resulting in a quiescenting of only that node. The SMI receiving node then polls other nodes in the multi-node computer to determine if the SMI affects an operation of any of the other nodes, and quiescents any other node affected by the SMI. Each quiescent node then transfers all of the contents of its system memory to a backup memory in an unaffected remote node in the multi-node computer. The remote node than assumes the function of the removed node that had received the SMI. The method and system thus allows node removal in the event of a hot-swap request or a predicted failure of a node.