Abstract: A sampling mechanism is disclosed in which software can specify a property or properties which characterize samples of interest. For example, if the software is interested in cache behavior, the software can specify that information for memory operations, or only information for memory instructions which miss in one or more caches, be reported. The sampling mechanism may specify many such properties and events (properties and events may vary from processor to processor, and may also depend on which properties or events are considered useful for performance analysis).

Abstract: A method of sampling instructions executing in a processor which includes selecting an instruction for sampling, gathering sampling information for the instruction, determining whether the instruction reissues during execution of the instruction, and storing reissue sample information if the instruction reissues during execution of the instruction. The method also includes storing certain sampling information as resettable sampling information and certain sampling information as persistent sampling information.

Abstract: A method of linking control transfer information with sampling information for instructions executing in a processor which includes storing information relating to execution events, selecting an instruction for sampling, storing information relating to the instruction for sampling, freezing the information relating to execution events when the information relating to the instruction for sampling is to be reported to provide frozen execution event information, reporting the information relating to the instruction for sampling, and enabling access to the frozen execution event information.

Abstract: A method of performance counting within a multi-threaded processor. The method includes counting events within the processor to provide an event count, and attributing the event count to events occurring within a thread of the processor or to events occurring globally within the processor.

Abstract: A method of sampling instructions executing in a multi-threaded processor which includes selecting an instruction for sampling, storing information relating to the instruction, determining whether the instruction includes an event of interest, and reporting the instruction if the instruction includes an event of interest on a per-thread basis. The event of interest includes information relating to a thread to which the instruction is bound.

Abstract: A sampling mechanism is disclosed in which software can specify a property or properties which characterize samples of interest. For example, if the software is interested in cache behavior, the software can specify that information for memory operations, or only information for memory instructions which miss in one or more caches, be reported. The sampling mechanism may specify many such properties and events (properties and events may vary from processor to processor, and may also depend on which properties or events are considered useful for performance analysis).

Abstract: An instruction fetch unit for fetching instructions from an instruction cache of a processor. The fetch unit includes a next fetch address mechanism generating predicted next fetch addresses, the next fetch address mechanism generating a next fetch address for a fetch bundle over at least two cycles of the processor. The next fetch address mechanism determines the next fetch address based on whether a control transfer instruction from an intermediate set of fetched instructions is taken.