Abstract: A method for using a storage array of a circuit includes generating a netlist of components and connections of circuitry of a storage array using behavioral description and random logic synthesis, using a write port to clock-gate each register of the storage array, and multiplexing data based on a selected word line of the storage array.

Abstract: A method for minimizing the skew (balancing) between all paths arriving at the inputs ports of each gate within a given combinatorial circuit.

Abstract: An FD-SOI GC-edRAM gain cell includes: a write bit line terminal connected to a WBL; a read bit line terminal connected to a RBL; a write trigger terminal connected to a WWL, for inputting a write trigger signal; a read trigger terminal put connected to a RWL, for inputting a read trigger signal; at least one body voltage terminal connected to a respective body voltage; and multiple FD-SOI transistors. The FD-SOI transistors are interconnected to form a storage node for retaining a data signal. The bodies of at least two of the transistors are coupled in a single well to a body voltage terminal. The write trigger signal triggers writing an input data signal from the write bit line terminal to the storage node and the read trigger signal triggers outputting the retained data signal from the storage node to the read bit line terminal.

Abstract: A method for minimizing the skew (balancing) between all paths arriving at the inputs ports of each gate within a given combinatorial circuit.

Abstract: A FinFET gain cell includes a write port, read port and storage node. The write port includes at least one write FinFET transistor and has write word-line (WWL) and write bit-line (WBL) inputs. The read port includes at least one FinFET read transistor and has a read word-line (RWL) input and a read bit-line (RBL) output. The storage node stores a data level written from said WBL. The storage nodes includes a single layer interconnect which connects the write port output diffusion connection to the read port input gate connection. The height of the single layer interconnect at the write port output diffusion connection is different from the height of the single layer interconnect at the read port input gate connection.

Abstract: An FD-SOI GC-edRAM gain cell includes: a write bit line terminal connected to a WBL; a read bit line terminal connected to a RBL; a write trigger terminal connected to a WWL, for inputting a write trigger signal; a read trigger terminal put connected to a RWL, for inputting a read trigger signal; at least one body voltage terminal connected to a respective body voltage; and multiple FD-SOI transistors. The FD-SOI transistors are interconnected to form a storage node for retaining a data signal. The bodies of at least two of the transistors are coupled in a single well to a body voltage terminal. The write trigger signal triggers writing an input data signal from the write bit line terminal to the storage node and the read trigger signal triggers outputting the retained data signal from the storage node to the read bit line terminal.

Abstract: A FinFET gain cell includes a write port, read port and storage node. The write port includes at least one write FinFET transistor and has write word-line (WWL) and write bit-line (WBL) inputs. The read port includes at least one FinFET read transistor and has a read word-line (RWL) input and a read bit-line (RBL) output. The storage node stores a data level written from said WBL. The storage nodes includes a single layer interconnect which connects the write port output diffusion connection to the read port input gate connection. The height of the single layer interconnect at the write port output diffusion connection is different from the height of the single layer interconnect at the read port input gate connection.

Abstract: A CDMR memory cell, includes a first bitcell which is used to store a current data level and a second bitcell which is used to store the complementary data level. When a read operation is performed, a comparator compares the data levels read from the two bitcells. If these two levels are not complementary, the comparator outputs an indicator. This indicator serves as an alert that a storage error has, or may have, occurred.

Abstract: A method uses data retention time (DRT) characteristics of a logic-compatible gain-cell embedded DRAM (dynamic random-access memory) (GC-eDRAM) array in a transistor circuit as a source for physical unclonable function (PUF) signature extraction of the circuit.

Abstract: A method of operating a first-in-first-out memory, called a FIFO, includes performing write and read operations of data with a FIFO. The FIFO has a size fifo_size and a maximum retention time. Once a datum is written to the FIFO, there is a limit of fifo_size-1 write operations before the datum becomes invalid and there is a limit of fifo_size-1 read operations before the datum is read, and the data is refreshed before reaching the maximum retention time. During the refreshing, the FIFO is available for further write and read operations.

Abstract: A method of operating a first-in-first-out memory, called a FIFO, includes performing write and read operations of data with a FIFO. The FIFO has a size fifo_size and a maximum retention time. Once a datum is written to the FIFO, there is a limit of fifo_size-1 write operations before the datum becomes invalid and there is a limit of fifo_size-1 read operations before the datum is read, and the data is refreshed before reaching the maximum retention time. During the refreshing, the FIFO is available for further write and read operations.

Abstract: A high-density memory includes: a data write interface, a data read interface, an array of memory cells and level-shifting write drivers. The data write interface inputs data written to the memory. The data read interface outputs data read from the memory. The array of memory cells stores data input at the data write interface and outputs stored data to the data read interface. Each of the memory cells includes at least one low threshold voltage (LVT) read transistor and at least one respective regular threshold voltage (RVT) transistor, so as to obtain high-speed read operations. The level-shifting write drivers supply shifted write wordline voltages to the array, so as to obtain high-speed write operations.

Abstract: A method uses data retention time (DRT) characteristics of a logic-compatible gain-cell embedded DRAM (dynamic random-access memory) (GC-eDRAM) array in a transistor circuit as a source for physical unclonable function (PUF) signature extraction of the circuit.

Abstract: A CDMR memory cell, includes a first bitcell which is used to store a current data level and a second bitcell which is used to store the complementary data level. When a read operation is performed, a comparator compares the data levels read from the two bitcells. If these two levels are not complementary, the comparator outputs an indicator. This indicator serves as an alert that a storage error has, or may have, occurred.

Abstract: A high-density memory includes: a data write interface, a data read interface, an array of memory cells and level-shifting write drivers. The data write interface inputs data written to the memory. The data read interface outputs data read from the memory. The array of memory cells stores data input at the data write interface and outputs stored data to the data read interface. Each of the memory cells includes at least one low threshold voltage (LVT) read transistor and at least one respective regular threshold voltage (RVT) transistor, so as to obtain high-speed read operations. The level-shifting write drivers supply shifted write wordline voltages to the array, so as to obtain high-speed write operations.

Abstract: A gain cell includes a write bit line input, a read bit line output, a write trigger input and a read trigger input. The write element writes a data level from the write bit line input to the gain cell when triggered by the write trigger input. The retention element buffers between an internal buffer node and an internal storage node during data retention. The retention element also connects or disconnects the buffer node to a first constant voltage according to the data level being retained in the gain cell. The read element decouples the storage node from the read bit line output during data read. The read element also connects and disconnects the read bit line output to a second constant voltage according to the data level being read from the gain cell.

Abstract: A gain cell includes a write bit line input, a read bit line output, a write trigger input and a read trigger input. The write element writes a data level from the write bit line input to the gain cell when triggered by the write trigger input. The retention element buffers between an internal buffer node and an internal storage node during data retention. The retention element also connects or disconnects the buffer node to a first constant voltage according to the data level being retained in the gain cell. The read element decouples the storage node from the read bit line output during data read. The read element also connects and disconnects the read bit line output to a second constant voltage according to the data level being read from the gain cell.

Abstract: A gain cell includes a write bit line input, a read bit line output, a write trigger input and a read trigger input. The gain cell also includes a write transistor, retention element and read transistor. Each of the transistors includes a respective first diffusion connection, gate connection and second diffusion connection. The write transistor first diffusion connection is connected to the write bit line input and the write transistor gate connection is connected to the write trigger input. The read transistor first diffusion connection being connected to the read bit line output and the second diffusion connection is connected to the read trigger input. The retention element buffers between write transistor and the read transistor during data retention. The retention element also connects or disconnects a write transistor diffusion connection to/from a constant voltage in accordance with a retained data level at the read transistor gate connection.

Abstract: A gain cell includes a write bit line input, a read bit line output, a write trigger input and a read trigger input. The gain cell also includes a write transistor, retention element and read transistor. Each of the transistors includes a respective first diffusion connection, gate connection and second diffusion connection. The write transistor first diffusion connection is connected to the write bit line input and the write transistor gate connection is connected to the write trigger input. The read transistor first diffusion connection being connected to the read bit line output and the second diffusion connection is connected to the read trigger input. The retention element buffers between write transistor and the read transistor during data retention. The retention element also connects or disconnects a write transistor diffusion connection to/from a constant voltage in accordance with a retained data level at the read transistor gate connection.

Abstract: A memory cell with an internal supply feedback loop is provided herein. The memory cell includes a latch having two storage nodes Q and QB, and a supply node. A gating device couples the supply node of the latch to the supply voltage. The gating device is controlled by a feedback loop coming from storage node QB. Due to the aforementioned asymmetric topology, the writing of logic “1” and the writing of logic “0” are carried out differently. Contrary to standard SRAM cells, in the hold states, only the QB storage node presents a valid value of stored data. The feedback loop cuts off the supply voltage for the latch such that the latch is no longer an inverting latch. By cutting off the supply voltage at the stable hold states, while maintaining readability of the memory cell, leakage currents associated with the hold states are eliminated altogether.