Abstract: A car may be equipped with a camera for detecting the movement of objects in the vicinity of the car. The camera may be used to capture a series of images. A number of target sample points may be defined in each image. The position of the target sample points may corresponding to the driver's blind spot or other region(s) of interest. The camera may also include separate filters for generating a long term pixel intensity output and a short term pixel intensity output at each of the target sample points. These long and short term average outputs may be compared to determine if a large change in intensity has occurred over a short period of time. The order of target activation can then be used to determine the direction of vehicle motion while filtering out noise or other road markings.

Abstract: A system includes a programmable logic device including a communication interface configured to receive an encrypted deep learning model and a first key in a bitstream. In an embodiment, the programmable logic device includes a storage block configured to store the first key. The programmable logic device also includes a decryption block configured to decrypt the deep learning model using the first key. A method includes receiving, at a programmable logic device, the encrypted deep learning model and a first key in a bitstream. The method also includes decrypting, at the programmable logic device, the deep learning model using the first key. The method also includes implementing the deep learning model on the programmable logic device.

Abstract: This disclosure relates generally to electronic design automation using high level synthesis techniques to generate circuit designs that include safety features. The algorithmic description representation can be specified in a first language and include at least one programming language construct associated with a first safety data type. Compiling the algorithmic description may involve identifying the at least one construct, accessing a first safety data type definition associated with the first safety data type, and generating a second representation of the circuit design based on the algorithmic description representation and the first safety data type definition. The second representation can be provided in a second language and include at least one safety feature for a portion of the circuit design associated with the at least one construct.

Abstract: Aspects of this disclosure relate generally to electronic design automation, and more specifically, to electronic design automation using high level synthesis techniques to generate circuit designs that include safety features. Some innovative aspects can be implemented in computer-readable media, systems and methods capable of accessing an algorithmic description representation of a circuit design. The algorithmic description representation can be specified in a first language and include at least one programming language construct associated with a first safety data type. The media, systems and methods also are capable of compiling the algorithmic description representation of the circuit design.

Abstract: A programmable integrated circuit may implement a safety function in a first region and a non-safety function in a second region of the programmable integrated circuit. The safety function may require that periodic tests verify the integrity of the programmable integrated circuit during safety test intervals. For this purpose, the programmable integrated circuit may halt the operation of the safety function, partially reconfigure the first region by loading a test function, and execute the test function, while the non-safety function in the second region continues to operate. In the event that the test function executed successfully without finding any defects, the programmable integrated circuit may partially reconfigure the first region by re-loading the safety function. Additional tests may be performed if the test function detected problems with the integrity of the programmable integrated circuit.

Abstract: This disclosure relates generally to electronic design automation using high level synthesis techniques to generate circuit designs that include safety features. The algorithmic description representation can be specified in a first language and include at least one programming language construct associated with a first safety data type. Compiling the algorithmic description may involve identifying the at least one construct, accessing a first safety data type definition associated with the first safety data type, and generating a second representation of the circuit design based on the algorithmic description representation and the first safety data type definition. The second representation can be provided in a second language and include at least one safety feature for a portion of the circuit design associated with the at least one construct.

Abstract: A car may be equipped with a camera for detecting the movement of objects in the vicinity of the car. The camera may be used to capture a series of images. A number of target sample points may be defined in each image. The position of the target sample points may corresponding to the driver's blind spot or other region(s) of interest. The camera may also include separate filters for generating a long term pixel intensity output and a short term pixel intensity output at each of the target sample points. These long and short term average outputs may be compared to determine if a large change in intensity has occurred over a short period of time. The order of target activation can then be used to determine the direction of vehicle motion while filtering out noise or other road markings.

Abstract: Aspects of this disclosure relate generally to electronic design automation, and more specifically, to electronic design automation using high level synthesis techniques to generate circuit designs that include safety features. Some innovative aspects can be implemented in computer-readable media, systems and methods capable of accessing an algorithmic description representation of a circuit design. The algorithmic description representation can be specified in a first language and include at least one programming language construct associated with a first safety data type. The media, systems and methods also are capable of compiling the algorithmic description representation of the circuit design.

Abstract: This disclosure relates generally to electronic design automation using high level synthesis techniques to generate circuit designs that include safety features. The algorithmic description representation can be specified in a first language and include at least one programming language construct associated with a first safety data type. Compiling the algorithmic description may involve identifying the at least one construct, accessing a first safety data type definition associated with the first safety data type, and generating a second representation of the circuit design based on the algorithmic description representation and the first safety data type definition. The second representation can be provided in a second language and include at least one safety feature for a portion of the circuit design associated with the at least one construct.

Abstract: A method for designing a system on a target device includes synthesizing a logic representation of a processing channel from a description of the processing channel in hardware description language (HDL) according to a first set of constraints. A logic representation for a redundant processing channel is synthesized from the description of the processing channel in HDL according to a second set of constraints. The processing channel and the redundant processing channel are placed and routed.

Abstract: This disclosure relates generally to field-programmable gate arrays (FPGAs). Some implementations relate to methods and systems for partitioning FPGA circuit designs to facilitate certification. In one aspect, a method includes generating a hardware description language (HDL) implementation of a circuit design. The method additionally includes partitioning the design into a first portion and a second portion. In some implementations, the second portion corresponds to a safety-critical portion of the design while the first portion corresponds to a non-safety-critical portion. The method additionally includes generating first configuration settings for the first portion and generating second configuration settings for the second portion. The method additionally includes verifying, or providing to a third-party certification body for verification, the first configuration settings for the first portion and the second configuration settings for the second portion.

Abstract: This disclosure relates generally to field-programmable gate arrays (FPGAs). Some implementations relate to methods and systems for partitioning FPGA circuit designs to facilitate certification. In one aspect, a method includes generating a hardware description language (HDL) implementation of a circuit design. The method additionally includes partitioning the design into a first portion and a second portion. In some implementations, the second portion corresponds to a safety-critical portion of the design while the first portion corresponds to a non-safety-critical portion. The method additionally includes generating first configuration settings for the first portion and generating second configuration settings for the second portion. The method additionally includes verifying, or providing to a third-party certification body for verification, the first configuration settings for the first portion and the second configuration settings for the second portion.

Abstract: This disclosure relates generally to field-programmable gate arrays (FPGAs). Some implementations relate to methods and systems for partitioning FPGA circuit designs to facilitate certification. In one aspect, a method includes generating a hardware description language (HDL) implementation of a circuit design. The method additionally includes partitioning the design into a first portion and a second portion. In some implementations, the second portion corresponds to a safety-critical portion of the design while the first portion corresponds to a non-safety-critical portion. The method additionally includes generating first configuration settings for the first portion and generating second configuration settings for the second portion. The method additionally includes verifying, or providing to a third-party certification body for verification, the first configuration settings for the first portion and the second configuration settings for the second portion.

Abstract: Techniques and circuits for testing a memory are provided. The techniques include disabling a plurality of interrupts to an integrated circuit (IC). Contents of a first memory region to be tested are copied to a second memory region. The second memory region where the contents are copied to is a safe memory region that will not be affected by the memory test. Memory accesses are mapped to the second memory region so that memory accesses that are associated with the first memory region are mapped to the second memory region. The plurality of interrupts is re-enabled after the memory contents in the first memory region are copied and remapped to the second memory region. Memory accesses due to the interrupts are redirected from the first memory region to the second memory region according to the memory mapping. The first memory region is tested with a test circuit of the IC.