Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers in the memory blocks. The channel-material strings directly electrically couple to conductor material of the conductor tier. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises a laterally-outer insulative lining extending longitudinally-along the immediately-laterally-adjacent memory-blocks. The laterally-outer insulative lining has its lowest surface between a top and a bottom of the lowest conductive tier. The laterally-outer insulative lining has its highest surface at or below a lowest surface of the next-lowest conductive tier.

Abstract: A memory array comprising strings of memory cells comprises a conductor tier comprising conductor material. Laterally-spaced memory blocks individually comprise a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Conducting material of a lower of the conductive tiers directly electrically coupling together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. The conducting material in the lower conductive tier comprises upper conductively-doped semiconductive material, lower conductively-doped semiconductive material, and intermediate material vertically there-between.

Abstract: Some embodiments include a structure having an opening extending into an integrated configuration. A first material is within the opening, and is configured to create an undulating topography relative to a sidewall of the opening. The undulating topography has a surface roughness characterized by a mean roughness parameter Rmean which is the mean peak-to-valley distance along the undulating topography. The Rmean is at least about 4 nm. A second material is within the opening and along at least a portion of the undulating topography. The first and second materials are compositionally different from one another. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier by conductive material of a lowest of the conductive tiers. Insulating material of the insulative tier that is immediately-directly above the lowest conductive tier is directly against a top of the conductive material of the lowest conductive tier. The insulating material comprises at least one of aluminum oxide, hafnium oxide, zirconium oxide, and carbon-doped insulative material. Other embodiments, including method, are disclosed.

Abstract: An electronic device comprises an array of memory cells comprising a channel material laterally proximate to tiers of alternating conductive materials and dielectric materials. The channel material comprises a heterogeneous semiconductive material varying in composition across a width thereof. Related electronic systems and methods are also disclosed.

Abstract: A microelectronic device comprises a stack structure, and slot structures vertically extending through the stack structure and dividing the stack structure into block structures. Each of the slot structures individually comprises an insulative liner material vertically extending though the slot structure and contacting sidewalls of the insulative levels and the conductive levels defining the slot structure, and grains of a material in contact with sidewalls of the insulative liner material. The grains of the material comprise first grains spanning an entire width between the sidewalls of the insulative liner material. Related memory devices, electronic systems, and methods are also described.

Abstract: An electronic device comprising a stack structure comprising one or more stacks of materials and a metal oxide material adjacent to the stacks of materials. The materials of the stacks comprise one or more chalcogenide materials. The metal oxide material comprises aluminum oxide, aluminum silicate, hafnium oxide, hafnium silicate, zirconium oxide, zirconium silicate, or a combination thereof and the metal oxide material extends continuously from an upper portion of the one or more stacks of materials to a lower portion of the one or more stacks of materials. Additional electronic devices are disclosed, as are related systems and methods of forming an electronic device.

Abstract: An electronic device comprising a stack structure comprising one or more stacks of materials and a metal oxide material adjacent to the stacks of materials. The materials of the stacks comprise one or more chalcogenide materials. The metal oxide material comprises aluminum oxide, aluminum silicate, hafnium oxide, hafnium silicate, zirconium oxide, zirconium silicate, or a combination thereof and the metal oxide material extends continuously from an upper portion of the one or more stacks of materials to a lower portion of the one or more stacks of materials. Additional electronic devices are disclosed, as are related systems and methods of forming an electronic device.

Abstract: An electronic device comprising a stack structure comprising one or more stacks of materials and a metal oxide material adjacent to the stacks of materials. The materials of the stacks comprise one or more chalcogenide materials. The metal oxide material comprises aluminum oxide, aluminum silicate, hafnium oxide, hafnium silicate, zirconium oxide, zirconium silicate, or a combination thereof and the metal oxide material extends continuously from an upper portion of the one or more stacks of materials to a lower portion of the one or more stacks of materials. Additional electronic devices are disclosed, as are related systems and methods of forming an electronic device.

Abstract: Some embodiments include a structure having an opening extending into an integrated configuration. A first material is within the opening, and is configured to create an undulating topography relative to a sidewall of the opening. The undulating topography has a surface roughness characterized by a mean roughness parameter Rmean which is the mean peak-to-valley distance along the undulating topography. The Rmean is at least about 4 nm. A second material is within the opening and along at least a portion of the undulating topography. The first and second materials are compositionally different from one another. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.

Abstract: An electronic device comprises an array of memory cells comprising a channel material laterally proximate to tiers of alternating conductive materials and dielectric materials. The channel material comprises a heterogeneous semiconductive material varying in composition across a width thereof. Related electronic systems and methods are also disclosed.

Abstract: A solid state light emitting device according to the present invention comprises an emitter structure having an active region of semiconductor material and a pair of oppositely doped layers of semiconductor material on opposite sides of said active region. The active region emits light at a first wavelength in response to an electrical bias across said doped layers. A quantum well structure is included that is integral to the emitter structure and has a plurality of layers having a composition and thickness such that the quantum well structure absorbs at least some of the light emitted from the active region and re-emits light of at least one different wavelength of light from said first wavelength.

Abstract: A solid state light emitting device comprising an emitter structure having an active region of semiconductor material and a pair of oppositely doped layers of semiconductor material on opposite sides of the active region. The active region emits light at a predetermined wavelength in response to an electrical bias across the doped layers. An absorption layer of semiconductor material is included that is integral to said emitter structure and doped with at least one rare earth or transition element. The absorption layer absorbs at least some of the light emitted from the active region and re-emits at least one different wavelength of light. A substrate is included with the emitter structure and absorption layer disposed on the substrate.

Abstract: The surface morphology of an LED light emitting surface is changed by applying a reactive ion etch (RIE) process to the light emitting surface. Etched features, such as truncated pyramids, may be formed on the emitting surface, prior to the RIE process, by cutting into the surface using a saw blade or a masked etching technique. Sidewall cuts may also be made in the emitting surface prior to the RIE process. A light absorbing damaged layer of material associated with saw cutting is removed by the RIE process. The surface morphology created by the RIE process may be emulated using different, various combinations of non-RIE processes such as grit sanding and deposition of a roughened layer of material or particles followed by dry etching.

Abstract: The surface morphology of an LED light emitting surface is changed by applying processes, such as a reactive ion etch (RIE) process to the light emitting surface. In one embodiment, the changed surface morphology takes the form of a moth-eye surface. The surface morphology created by the RIE process may be emulated using different combinations of non-RIE processes such as grit sanding and deposition of a roughened layer of material or particles followed by dry etching.

Abstract: The surface morphology of an LED light emitting surface is changed by applying processes, such as a reactive ion etch (RIE) process to the light emitting surface. In one embodiment, the changed surface morphology takes the form of a moth-eye surface. The surface morphology created by the RIE process may be emulated using different combinations of non-RIE processes such as grit sanding and deposition of a roughened layer of material or particles followed by dry etching.

Abstract: The surface morphology of an LED light emitting surface is changed by applying processes, such as a reactive ion etch (RIE) process to the light emitting surface. In one embodiment, the changed surface morphology takes the form of a moth-eye surface. The surface morphology created by the RIE process may be emulated using different combinations of non-RIE processes such as grit sanding and deposition of a roughened layer of material or particles followed by dry etching.

Abstract: The surface morphology of an LED light emitting surface is changed by applying a reactive ion etch (RIE) process to the light emitting surface. Etched features, such as truncated pyramids, may be formed on the emitting surface, prior to the RIE process, by cutting into the surface using a saw blade or a masked etching technique. Sidewall cuts may also be made in the emitting surface prior to the RIE process. A light absorbing damaged layer of material associated with saw cutting is removed by the RIE process. The surface morphology created by the RIE process may be emulated using different, various combinations of non-RIE processes such as grit sanding and deposition of a roughened layer of material or particles followed by dry etching.

Abstract: A method of forming a high-power, high-frequency device in wide bandgap semiconductor materials with reduced junction temperature, higher power density during operation and improved reliability at a rated power density is disclosed, along with resulting semiconductor structures and devices. The method includes adding a layer of diamond to a silicon carbide wafer to increase the thermal conductivity of the resulting composite wafer, thereafter reducing the thickness of the silicon carbide portion of the composite wafer while retaining sufficient thickness of silicon carbide to support epitaxial growth thereon, preparing the silicon carbide surface of the composite wafer for epitaxial growth thereon, and adding a Group III nitride heterostructure to the prepared silicon carbide face of the wafer.