Patents by Inventor Adam Welc
Adam Welc has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9336066Abstract: A method and apparatus for hybrid validation for a Software Transaction Memory (STM) is herein described. During execution of a transaction, when acquiring ownership of meta-data associated with a data element, the meta-data is updated with an ownership reference to a transaction to enable efficient subsequent ownership tests. However, during validation, for some conditions, meta-data is updated from the ownership reference to a write entry reference to enable efficient validation.Type: GrantFiled: June 19, 2008Date of Patent: May 10, 2016Assignee: Intel CorporationInventors: Adam Welc, Bratin Saha, Ali-Reza Adl-Tabatabai
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Patent number: 9052947Abstract: A method and apparatus for unified concurrency control in a Software Transactional Memory (STM) is herein described. A transaction record associated with a memory address referenced by a transactional memory access operation includes optimistic and pessimistic concurrency control fields. Access barriers and other transactional operations/functions are utilized to maintain both fields of the transaction record, appropriately. Consequently, concurrent execution of optimistic and pessimistic transactions is enabled.Type: GrantFiled: September 16, 2013Date of Patent: June 9, 2015Assignee: Intel CorporationInventors: Ali-Reza Adl-Tabatabai, Moshe Bach, Sion Berkowits, James Henry Cownie, Yang Ni, Jeffrey V. Olivier, Bratin Saha, Ady Tal, Adam Welc
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Patent number: 8954986Abstract: Methods, systems, and mediums are described for scheduling data parallel tasks onto multiple thread execution units of processing system. Embodiments of a lock-free queue structure and methods of operation are described to implement a method for scheduling fine-grained data-parallel tasks for execution in a computing system. The work of one of a plurality of worker threads is wait-free with respect to the other worker threads. Each node of the queue holds a reference to a task that may be concurrently performed by multiple thread execution units, but each on a different subset of data. Various embodiments relate to software-based scheduling of data-parallel tasks on a multi-threaded computing platform that does not perform such scheduling in hardware. Other embodiments are also described and claimed.Type: GrantFiled: December 17, 2010Date of Patent: February 10, 2015Assignee: Intel CorporationInventors: Mohan Rajagopalan, Ali-Reza Adl-Tabatabai, Yang Ni, Adam Welc, Richard L. Hudson
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Publication number: 20140156953Abstract: A method and apparatus for unified concurrency control in a Software Transactional Memory (STM) is herein described. A transaction record associated with a memory address referenced by a transactional memory access operation includes optimistic and pessimistic concurrency control fields. Access barriers and other transactional operations/functions are utilized to maintain both fields of the transaction record, appropriately. Consequently, concurrent execution of optimistic and pessimistic transactions is enabled.Type: ApplicationFiled: September 16, 2013Publication date: June 5, 2014Inventors: Ali-Reza Adl-Tabatabai, Moshe Bach, Sion Berkowits, James Henry Cownie, Yang Ni, Jeffrey V. Olivier, Bratin Saha, Ady Tal, Adam Welc
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Patent number: 8627048Abstract: A method and apparatus for designating and handling irrevocable transactions is herein described. In response to detecting an irrevocable event, such as an I/O operation, a user-defined irrevocable designation, and a dynamic failure profile, a transaction is designated as irrevocable. In response to designating a transaction as irrevocable, Single Owner Read Locks (SORLs) are acquired for previous and subsequent reads in the irrevocably designated transaction to ensure the transaction is able to complete without modification to locations read from, while permitting remote resources to load from those locations to continue execution.Type: GrantFiled: September 13, 2011Date of Patent: January 7, 2014Assignee: Intel CorporationInventors: Adam Welc, Bratin Saha, Ali-Reza Adl-Tabatabai
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Publication number: 20120159495Abstract: Methods, systems, and mediums are described for scheduling data parallel tasks onto multiple thread execution units of processing system. Embodiments of a lock-free queue structure and methods of operation are described to implement a method for scheduling fine-grained data-parallel tasks for execution in a computing system. The work of one of a plurality of worker threads is wait-free with respect to the other worker threads. Each node of the queue holds a reference to a task that may be concurrently performed by multiple thread execution units, but each on a different subset of data. Various embodiments relate to software-based scheduling of data-parallel tasks on a multi-threaded computing platform that does not perform such scheduling in hardware. Other embodiments are also described and claimed.Type: ApplicationFiled: December 17, 2010Publication date: June 21, 2012Inventors: Mohan Rajagopalan, Ali-Reza Adl-Tabatabai, Yang Ni, Adam Welc, Richard L. Hudson
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Patent number: 8195898Abstract: A method and apparatus for a hybrid transactional memory system is herein described. A first transaction is executed utilizing a first style of a transactional memory system and a second transaction is executed in parallel utilizing a second style of a transactional memory system. For example, a main thread is executed utilizing an update-in place Software Transactional Memory (STM) system while a parallel thread, such as a helper thread, is executed utilizing a write buffering STM. As a result, a main thread may directly update memory locations, while a helper thread's transactional writes are buffered to ensure they do not invalidate transactional reads of the main thread. Therefore, parallel execution of threads is achieved, while ensuring at least one thread, such as a main thread, does not degrade below an amount of execution cycles it would take to execute the main thread serially.Type: GrantFiled: December 27, 2007Date of Patent: June 5, 2012Assignee: Intel CorporationInventors: Adam Welc, Ali-Reza Adl-Tabatabai
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Publication number: 20110320776Abstract: A method and apparatus for designating and handling irrevocable transactions is herein described. In response to detecting an irrevocable event, such as an I/O operation, a user-defined irrevocable designation, and a dynamic failure profile, a transaction is designated as irrevocable. In response to designating a transaction as irrevocable, Single Owner Read Locks (SORLs) are acquired for previous and subsequent reads in the irrevocably designated transaction to ensure the transaction is able to complete without modification to locations read from, while permitting remote resources to load from those locations to continue execution.Type: ApplicationFiled: September 13, 2011Publication date: December 29, 2011Inventors: Adam Welc, Bratin Saha, Ali-Reza Adl-Tabatabai
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Patent number: 8086827Abstract: A method and apparatus for designating and handling irrevocable transaction is herein described. In response to detecting an irrevocable event, such as an I/O operation, a user-defined irrevocable designation, and a dynamic failure profile, a transaction is designated as irrevocable. In response to designating a transaction as irrevocable, Single Owner Read Locks (SORLs) are acquired for previous and subsequent reads in the irrevocably designated transaction to ensure the transaction is able to complete without modification to locations read from, while permitting remote resources to load from those locations to continue execution.Type: GrantFiled: December 28, 2006Date of Patent: December 27, 2011Assignee: Intel CorporationInventors: Adam Welc, Bratin Saha, Ali-Reza Adl-Tabatabai
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Patent number: 7770157Abstract: A system, method, and computer readable medium, for automatically improving performance of, and optimizing, a program based on on-line profile data of the program and profile data (302) collected across multiple runs of the program and stored in a persistent off-line repository (114). The method includes executing a program in an execution environment. Profile data (302) is collected for the program across multiple runs thereof. The performance of the program is improved, such as by optimization of the program, based on on-line profile data of the executing program and the collected profile data in the persistent off-line repository.Type: GrantFiled: August 8, 2005Date of Patent: August 3, 2010Assignee: International Business Machines CorporationInventors: Matthew R. Arnold, Vadakkedathu T. Rajan, Adam Welc
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Publication number: 20100162247Abstract: Methods and systems for executing nested concurrent threads of a transaction are presented. In one embodiment, in response to executing a parent transaction, a first group of one or more concurrent threads including a first thread is created. The first thread is associated with a transactional descriptor comprising a pointer to the parent transaction.Type: ApplicationFiled: December 19, 2008Publication date: June 24, 2010Inventors: Adam Welc, Haris Volos, Ali Adl-Tabatabai, Tatiana Shpeisman
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Publication number: 20090319753Abstract: A method and apparatus for hybrid validation for a Software Transaction Memory (STM) is herein described. During execution of a transaction, when acquiring ownership of meta-data associated with a data element, the meta-data is updated with an ownership reference to a transaction to enable efficient subsequent ownership tests. However, during validation, for some conditions, meta-data is updated from the ownership reference to a write entry reference to enable efficient validation.Type: ApplicationFiled: June 19, 2008Publication date: December 24, 2009Inventors: Adam Welc, Bratin Saha, Ali-Reza Adl-Tabatabai
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Publication number: 20090172303Abstract: A method and apparatus for a hybrid transactional memory system is herein described. A first transaction is executed utilizing a first style of a transactional memory system and a second transaction is executed in parallel utilizing a second style of a transactional memory system. For example, a main thread is executed utilizing an update-in place Software Transactional Memory (STM) system while a parallel thread, such as a helper thread, is executed utilizing a write buffering STM. As a result, a main thread may directly update memory locations, while a helper thread's transactional writes are buffered to ensure they do not invalidate transactional reads of the main thread. Therefore, parallel execution of threads is achieved, while ensuring at least one thread, such as a main thread, does not degrade below an amount of execution cycles it would take to execute the main thread serially.Type: ApplicationFiled: December 27, 2007Publication date: July 2, 2009Inventors: Adam Welc, Ali-Reza Adl-Tabatabai
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Publication number: 20080162881Abstract: A method and apparatus for designating and handling irrevocable transaction is herein described. In response to detecting an irrevocable event, such as an I/O operation, a user-defined irrevocable designation, and a dynamic failure profile, a transaction is designated as irrevocable. In response to designating a transaction as irrevocable, Single Owner Read Locks (SORLs) are acquired for previous and subsequent reads in the irrevocably designated transaction to ensure the transaction is able to complete without modification to locations read from, while permitting remote resources to load from those locations to continue execution.Type: ApplicationFiled: December 28, 2006Publication date: July 3, 2008Inventors: Adam Welc, Bratin Saha, Ali-Reza Adl-Tabatabai
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Publication number: 20070033578Abstract: A system, method, and computer readable medium, for automatically improving performance of, and optimizing, a program based on on-line profile data of the program and profile data (302) collected across multiple runs of the program and stored in a persistent off-line repository (114). The method includes executing a program in an execution environment. Profile data (302) is collected for the program across multiple runs thereof. The performance of the program is improved, such as by optimization of the program, based on on-line profile data of the executing program and the collected profile data in the persistent off-line repository.Type: ApplicationFiled: August 8, 2005Publication date: February 8, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew Arnold, Vadakkedathu Rajan, Adam Welc