Patents by Inventor Adam Wright

Adam Wright has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070137576
    Abstract: A technique for providing an inductively coupled radio frequency plasma flood gun is disclosed. In one particular exemplary embodiment, the technique may be realized as a plasma flood gun in an ion implantation system. The plasma flood gun may comprise: a plasma chamber having one or more apertures; a gas source capable of supplying at least one gaseous substance to the plasma chamber; and a power source capable of inductively coupling radio frequency electrical power into the plasma chamber to excite the at least one gaseous substance to generate a plasma. Entire inner surface of the plasma chamber may be free of metal-containing material and the plasma may not be exposed to any metal-containing component within the plasma chamber. In addition, the one or more apertures may be wide enough for at least one portion of charged particles from the plasma to flow through.
    Type: Application
    Filed: March 16, 2006
    Publication date: June 21, 2007
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Peter F. Kurunczi, Russell Low, Alexander S. Perel, Eric R. Cobb, Ethan Adam Wright
  • Publication number: 20070084607
    Abstract: A safety valve system includes a safety valve having an actuator and a line connected to the actuator. The safety valve is operable by opening the line in the well, with the line being free of any connection to a surface control system. Another safety valve system includes multiple safety valves. An actuator of each safety valve is connected to an actuator of another safety valve via a line. A biasing force in each of the actuators is operative to close the respective one of the safety valves in response to opening of the line. The biasing force is produced at least in part by hydrostatic pressure in a well.
    Type: Application
    Filed: October 19, 2005
    Publication date: April 19, 2007
    Inventors: Adam Wright, Vincent Zeller, Harold Nivens, Roger Schultz
  • Publication number: 20070079968
    Abstract: A hydraulic control and actuation system for downhole tools. In a described embodiment, a hydraulic control and actuation system includes an internal chamber serving as a low pressure region and a well annulus serving as an energy source. A valve assembly provides selective fluid communication between alternating opposite sides of a piston and each of the energy source and low pressure region. Displacement of the piston operates a well tool. Operation of the valve assembly is controlled via telemetry between a remote location and an electronic circuit of the system.
    Type: Application
    Filed: October 18, 2006
    Publication date: April 12, 2007
    Inventors: Roger Schultz, Melissa Allin, Paul Ringgenberg, Vincent Zeller, Tyler Trinh, Adam Wright, Donald Kyle
  • Publication number: 20070029078
    Abstract: A multicycle hydraulic control valve. A control and actuation system for a well tool includes a control valve having one or more metal-to-metal seals which open while differential pressure exists across the seals to thereby selectively connect pressure sources to an actuator to operate the well tool. Both seals may be closed while a connection between the actuator and the pressure sources is switched by the control valve. The control valve may include a member having areas formed thereon acted upon by various pressures to facilitate operation of the control valve.
    Type: Application
    Filed: August 8, 2005
    Publication date: February 8, 2007
    Inventors: Adam Wright, Roger Schultz
  • Patent number: 7103813
    Abstract: A bridging fault detection system allows for a high amount of test coverage using a low number of test configurations. The bridging fault detection system automatically creates optimal test configurations and test vectors without the need for precise layout information, and is adaptable to complex programmable device architectures. Testers can specify a precise level of testing coverage to optimize the testing processing. A programmable device with interconnect bias circuitry decreases the number of test configurations and thus the time needed to test for bridging faults. The interconnect bias circuit provides explicit test control over the unused lines in a configuration, driving them both high and low for complete test coverage between each line and all of its possible neighbors. The bridging fault detection system balances the available number of control test points against the number of interconnect segments stitched together by programmable connection to maximize the lines under test per configuration.
    Type: Grant
    Filed: November 6, 2003
    Date of Patent: September 5, 2006
    Assignee: Altera Corporation
    Inventors: Paul Tracy, Anthony Pang, Andy Lee, Adam Wright, Rahul Saini
  • Patent number: 7024327
    Abstract: Programmable circuits have a programmable interconnect structure that connects programmable circuit elements. Tests patterns can be automatically generated for the programmable circuit elements and interconnections on a programmable circuit. A connectivity graph represents programmable interconnections and functions as nodes. Tests routes are generated that connect the nodes in the connectivity graph between control points and observation points on the programmable circuit. The routes are grouped into configuration patterns that can be tested in one test cycle. Test vectors are then applied to the routes to determine if the interconnects and circuit functions are operable. Systems and methods of the present invention automatically create test patterns for a programmable circuit to reduce engineer time. The present invention also reduces test time and resources by increasing the number of interconnections and circuit elements tested in each configuration pattern.
    Type: Grant
    Filed: December 18, 2002
    Date of Patent: April 4, 2006
    Assignee: Altera Corporation
    Inventors: Jayabrata Ghosh Dastidar, Adam Wright, Hung Hing Anthony Pang, Binh Vo, Ajay Nagarandal, Paul J. Tracy, Michael Harms
  • Patent number: 7020582
    Abstract: Systems and methods are provided for marking integrated circuit defects on wafers to facilitate failure analysis. A wafer containing integrated circuits can be tested using a tester. Test data from the tester can be analyzed using integrated circuit design files to identify suspected faults. A fault location program can be used to identify the physical location of the faults. The fault location program uses information on the faults identified and CAD file information on the physical layout of the integrated circuit to map identified faults to actual physical positions. The fault location program may also generate laser control files. The laser control files can be used to control a laser system so that the laser system creates laser marks on the wafer surrounding each of the faults. The marked faults can be polished and examined under an electron microscope or analyzed using other failure analysis tools.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: March 28, 2006
    Assignee: Altera Corporation
    Inventors: John M. Dicosola, Adam Wright, Junzhao J. Lei, Mark A. Banke, William Hata
  • Publication number: 20060037746
    Abstract: A downhole oil and water separator for an oil well includes a water-selective membrane disposed in a production flowpath of the well. The water-selective membrane is operable to selectively pass water from the production flowpath to a disposal zone to increase the concentration of oil in the production flowpath at the surface.
    Type: Application
    Filed: August 23, 2004
    Publication date: February 23, 2006
    Inventors: Adam Wright, Roger Schultz, Syed Hamid, Harry Smith
  • Patent number: 6938236
    Abstract: A method for creating a mask-programmed device from a preexisting design of a source device is provided. The method includes creating a netlist from a user defined circuit configuration file, configuring logic resources on the mask-programmed device produce basic logic elements, and generating a custom interconnect based on the netlist that interconnects the configured logic resources to produce the desired logic design.
    Type: Grant
    Filed: March 29, 2002
    Date of Patent: August 30, 2005
    Assignee: Altera Corporation
    Inventors: Jonathan Park, Eugen Chen, Richard Saito, Adam Wright, Evgueni Ratchev
  • Publication number: 20050022085
    Abstract: Techniques are provided for isolating failed routing resources on a programmable circuit. Failing test patterns and the test logs are fed to a Statistical Failure Isolation (SFI) tool. The SFI tool extracts failing paths from the test patterns. A statistical analysis is performed on interconnect resources related to failing paths. The resources on the paths are then tallied to create a histogram of resources. These resources are then be fed into an Adaptive Failure Isolation (AFI) tool to auto-generate verification patterns. A tester uses the verification patterns to isolate failed interconnect resources.
    Type: Application
    Filed: October 30, 2003
    Publication date: January 27, 2005
    Applicant: Altera Corporation
    Inventors: Binh Vo, Wan-Pin Hung, David Huang, Peter Boyle, Qi Chen, Kaiyu Ren, Adam Wright, John DiCosola, Laiq Chughtai, Seng Lim
  • Publication number: 20040168805
    Abstract: A system and method of damping fluid pressure waves in a subterranean well. In a described embodiment, pressure waves are damped by positioning a dampener in the well during a perforating operation. The dampener may attenuate the pressure waves by absorbing the pressure waves, flowing the pressure waves through viscously damping material, generating complementary pressure waves, changing a material phase, or by a combination of these methods.
    Type: Application
    Filed: February 28, 2003
    Publication date: September 2, 2004
    Inventors: Michael L. Fripp, Adam Wright
  • Patent number: 6625771
    Abstract: An improved method of simulating the testing of integrated circuits is provided. A database of desired connections between a tester unit and a DUT for different downbonds is accessed by a multiplexer which sets up the desired connections. The system automatically makes the correct connection for each downbond without manual intervention from the user as was required in traditional simulator systems.
    Type: Grant
    Filed: March 22, 2001
    Date of Patent: September 23, 2003
    Assignee: Altera Corporation
    Inventor: Adam Wright
  • Publication number: 20020019963
    Abstract: An improved method of simulating the testing of integrated circuits is provided. A database of desired connections between a tester unit and a DUT for different downbonds is accessed by a multiplexer which sets up the desired connections. The system automatically makes the correct connection for each downbond without manual intervention from the user as was required in traditional simulator systems.
    Type: Application
    Filed: March 22, 2001
    Publication date: February 14, 2002
    Inventor: Adam Wright
  • Patent number: 6247155
    Abstract: An improved method of simulating the testing of integrated circuits is provided. A database of desired connections between a tester unit and a DUT for different downbonds is accessed by a multiplexer which sets up the desired connections. The system automatically makes the correct connection for each downbond without manual intervention from the user as was required in traditional simulator systems.
    Type: Grant
    Filed: March 4, 1999
    Date of Patent: June 12, 2001
    Assignee: Altera Corporation
    Inventor: Adam Wright
  • Patent number: 6112020
    Abstract: An apparatus and method for generating configuration and test files for programmable logic devices includes a dynamic configuration and test generation program to specify, in source code, a logic function to be implemented by a programmable logic device. A device test development kernel program has information characterizing physical elements of the programmable logic device and bit patterns for implementing connections between the physical elements of the programmable logic device. The device test development kernel program converts the logic function into a configuration file for use in programming the logic function into the programmable logic device. The dynamic configuration and test generation program also specifies, in source code, a test operation to be executed by the programmable logic device. It operates with the device test development kernel program to produce a vector file for use in testing the programmable logic device.
    Type: Grant
    Filed: May 27, 1997
    Date of Patent: August 29, 2000
    Assignee: Altera Corporation
    Inventor: Adam Wright
  • Patent number: 5909450
    Abstract: An improved method of simulating the testing of integrated circuits is provided. A database of desired connections between a tester unit and a DUT for different downbonds is accessed by a multiplexer which sets up the desired connections. The system automatically makes the correct connection for each downbond without manual intervention from the user as was required in traditional simulator systems.
    Type: Grant
    Filed: November 14, 1997
    Date of Patent: June 1, 1999
    Assignee: Altera Corporation
    Inventor: Adam Wright
  • Patent number: 4427718
    Abstract: A method of encapsulating a cable strand formed of a plurality of bundled steel wires is carried out by forcing apart the wires of the strand with wooden wedges, and then filling the resulting gap solid with red lead paste. After this, the wedges are removed to permit the paste to coat and fill all voids between the strand wires. This operation is repeated at a plurality of circumferential positions on the strand. Then, the wedges can be driven in at an adjacent position up the strand. Next, the portion of the strand at which the red lead paste has been so applied is coated with the same paste. Finally, the cable is paint encapsulated by using a bath of red lead paint. This method is favorably carried out to protect the crotch of a suspension bridge main cable strand at a position near the strand shoe thereof.
    Type: Grant
    Filed: May 27, 1982
    Date of Patent: January 24, 1984
    Inventors: Patrick Heron, Timothy Hartnett, Adam Wright