Abstract: A memory architecture includes a memory including a Command Set, and a serial peripheral interface (SPI) for connecting the memory to a generic host device. The SPI includes a data in line for supplying output data from the host device to inputs of the memory; a data out line for supplying output data from the memory to input of the host device; a clock line driven by the host device; and an enable line that allows the memory to be turned on and off by the host device. The memory is a NAND Flash Memory. The SPI includes an I/O registers block, including an SPI label register and a data register for driving separately data, commands and addresses directed to the memory from the corresponding SPI label registers.

Abstract: A method of managing fails in a non-volatile memory device including an array of cells grouped in blocks of data storage cells includes defining in the array a first subset of user addressable blocks of cells, and a second subset of redundancy blocks of cells. A third subset of non-user addressable blocks of cells is defined in the array for storing the bad block address table of respective codes in an addressable page of cells of a block of the third subset. Each page of the third subset is associated to a corresponding redundancy block. If during the working life of the memory device a block of cells previously judged good in a test phase becomes failed, each block is marked as bad and the stored table in the random access memory is updated.

Abstract: A memory architecture includes a memory including a Command Set, and a serial peripheral interface (SPI) for connecting the memory to a generic host device. The SPI includes a data in line for supplying output data from the host device to inputs of the memory; a data out line for supplying output data from the memory to input of the host device; a clock line driven by the host device; and an enable line that allows the memory to be turned on and off by the host device. The memory is a NAND Flash Memory. The SPI includes an I/O registers block, including an SPI label register and a data register for driving separately data, commands and addresses directed to the memory from the corresponding SPI label registers.

Abstract: A method of managing fails in a non-volatile memory device including an array of cells grouped in blocks of data storage cells includes defining in the array a first subset of user addressable blocks of cells, and a second subset of redundancy blocks of cells. Each block including at least one failed cell in the first subset is located during a test on wafer of the non-volatile memory device. Each block is marked as bad, and a bad block address table of respective codes is stored in a non-volatile memory buffer. At power-on, the bad block address table is copied from the non-volatile memory buffer to the random access memory. A block of memory cells of the first subset is verified as bad by looking up the bad block address table, and if a block is bad, then remapping access to a corresponding block of redundancy cells.