Abstract: A channel-less design-for-test (DFT) architecture implements distributed test functionality across hardware modules (HMs) of an integrated circuit. The architecture includes a center HM and peripheral HMs interconnected by a standardized bus that carries DFT data communication. Each HM incorporates DFT circuitry comprising a scan shift network (SSN) and an encoder/decoder for test (EDT) circuit to perform local test operations. The center HM includes SSN multiplexing circuitry that manages SSN connections for coordinated test operations across the HMs. This distributed architecture eliminates the need for dedicated test routing channels between modules while enabling independent DFT operations within each HM. The standardized bus interface reduces routing complexity and supports efficient test data communication between modules.