Abstract: In one embodiment, a system comprises: a global clock input for receiving a global clock, a plurality of partitions; and a skew tolerant interface configured to compensate for clock skew differences between a global clock from outside at least one of the partitions and a balanced local clock within at least one of the partitions. The partitions can be test partitions. The skew tolerant interface can cross a mesochronous boundary. In one exemplary implementation, the skew tolerant interface includes a deskew ring buffer on communication path of the at least one partition. pointers associated with the ring buffer can be free-running and depend only on clocks being pulsed when out of reset. The scheme can be fully synchronous and deterministic. The scheme can be modeled for the ATPG tools using simple pipeline flops. The depth of the pipeline can be dependent on the pointer difference for the read/write interface. The global clock input can be part of a scan link.

Abstract: In one embodiment, a system comprises: a global clock input for receiving a global clock, a plurality of partitions; and a skew tolerant interface configured to compensate for clock skew differences between a global clock from outside at least one of the partitions and a balanced local clock within at least one of the partitions. The partitions can be test partitions. The skew tolerant interface can cross a mesochronous boundary. In one exemplary implementation, the skew tolerant interface includes a deskew ring buffer on communication path of the at least one partition. pointers associated with the ring buffer can be free-running and depend only on clocks being pulsed when out of reset. The scheme can be fully synchronous and deterministic. The scheme can be modeled for the ATPG tools using simple pipeline flops. The depth of the pipeline can be dependent on the pointer difference for the read/write interface. The global clock input can be part of a scan link.

Abstract: According to an aspect of the present invention, one of multiple clock signals of different relative phases is selected based on a desired delay magnitude, and the digital values received on an input signal are then synchronized to an edge (“first edge”) of the selected clock signal to provide the digital values with the desired delay magnitude. In an embodiment, the selected clock signal can be delayed by a fine value (less than the minimum phase difference of the multiple clock signals) to provide a wide span of desired delays. An aspect of the invention provides for a synchronization circuit with reduced latency and which is substantially invariant to process, voltage and temperature (PVT) changes.

Abstract: According to an aspect of the present invention, one of multiple clock signals of different relative phases is selected based on a desired delay magnitude, and the digital values received on an input signal are then synchronized to an edge (“first edge”) of the selected clock signal to provide the digital values with the desired delay magnitude. In an embodiment, the selected clock signal can be delayed by a fine value (less than the minimum phase difference of the multiple clock signals) to provide a wide span of desired delays. An aspect of the invention provides for a synchronization circuit with reduced latency and which is substantially invariant to process, voltage and temperature (PVT) changes.

Abstract: A testing device uses an input signature register to conduct “at speed” testing of asynchronous circuit responses in an effort to determine the operability of a monitored circuit. Upon receiving an enable signal, the input signature register quickly measures, compresses, and transmits the tested circuit responses so that the responses can be compared with a set of anticipated responses to determine whether the circuit is functioning properly. The enabled input signature register, such as a MISR or a SISR, generates an output signature, which contains the compressed responses of the monitored circuit and helps the testing device analyze circuit performance.

Abstract: A testing device uses an input signature register to conduct “at speed” testing of asynchronous circuit responses in an effort to determine the operability of a monitored circuit. Upon receiving an enable signal, the input signature register quickly measures, compresses, and transmits the tested circuit responses so that the responses can be compared with a set of anticipated responses to determine whether the circuit is functioning properly. The enabled input signature register, such as a MISR or a SISR, generates an output signature, which contains the compressed responses of the monitored circuit and helps the testing device analyze circuit performance.