Patents by Inventor Adarsh Panikkar
Adarsh Panikkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8098783Abstract: Some embodiments of the invention provide a biased tracking loop that may include encoded information. Embodiments may comprise a training pattern, utilized in a non-interfering way that allows for clock recovery, embedded information transmission and/or header alignment. Therefore, embodiments may comprise a tracking loop training pattern that comprises data.Type: GrantFiled: April 28, 2008Date of Patent: January 17, 2012Assignee: Intel CorporationInventors: Adarsh Panikkar, Kersi H. Vakil, Pete D. Vogt
-
Patent number: 7672335Abstract: A method is described that involves loading X bits at a time into a shift register and shifting groups of older, loaded X bits up in the shift register with each new group of loaded X bits. Each group of X bits has been received from a serial data stream. The method further involves identifying an alignment key within the shift register and presenting aligned data from the serial data stream by rotating selection of a first group of Y contiguous bits from the shift register and a second group of Y contiguous bits from the shift register after the identifying. Y is greater than X.Type: GrantFiled: December 10, 2003Date of Patent: March 2, 2010Assignee: Intel CorporationInventors: Adarsh Panikkar, Wayne C. Ashby, Abhimanyu Kolla
-
Patent number: 7656983Abstract: In general, in one aspect, the disclosure describes an apparatus including a first deskew unit and a second deskew unit. The first deskew unit operates at a first clock domain and provides fine timing adjustment to a signal. The second deskew unit operates at a second clock domain that is slower than the first clock domain and provide coarse timing adjustment to the signal.Type: GrantFiled: September 29, 2006Date of Patent: February 2, 2010Assignee: Intel CorporationInventors: Daniel S. Klowden, S. Reji Kumar, Adarsh Panikkar, Kersi H. Vakil, Abhimanyu Kolla
-
Patent number: 7500131Abstract: Some embodiments of the invention provide a training sequence that may be used in a deskewing process or a protocol to be implemented in a training sequence deskew. Embodiments may also comprise a training pattern that allows for header or frame alignment.Type: GrantFiled: September 7, 2004Date of Patent: March 3, 2009Assignee: Intel CorporationInventors: Adarsh Panikkar, S. Reji Kumar, Daniel Klowden, Abhimanyu Kolla
-
Patent number: 7466723Abstract: Various methods, apparatuses and systems are described in which a skew delay time between communication lanes is determined. A data transfer path is established which includes two or more communication lanes in a communication link. A skew delay time is determined between the communication lanes of the communication link with respect each other with using a clock period of a input output circuit as a reference time.Type: GrantFiled: June 29, 2004Date of Patent: December 16, 2008Assignee: Intel CorporationInventors: Kersi H. Vakil, Adarsh Panikkar
-
Publication number: 20080260082Abstract: Some embodiments of the invention provide a biased tracking loop that may include encoded information. Embodiments may comprise a training pattern, utilized in a non-interfering way that allows for clock recovery, embedded information transmission and/or header alignment. Therefore, embodiments may comprise a tracking loop training pattern that comprises data.Type: ApplicationFiled: April 28, 2008Publication date: October 23, 2008Inventors: Adarsh Panikkar, Kersi H. Vakil, Pete D. Vogt
-
Publication number: 20080130815Abstract: Embodiments to selectively track serial communication link data are presented herein.Type: ApplicationFiled: December 5, 2006Publication date: June 5, 2008Inventors: S. Reji Kumar, Arnaud Forestier, Adarsh Panikkar, Kersi H. Vakil
-
Patent number: 7369634Abstract: Some embodiments of the invention provide a biased tracking loop that may include encoded information. Embodiments may comprise a training pattern, utilized in a non-interfering way that allows for clock recovery, embedded information transmission and/or header alignment. Therefore, embodiments may comprise a tracking loop training pattern that comprises data.Type: GrantFiled: September 7, 2004Date of Patent: May 6, 2008Assignee: Intel CorporationInventors: Adarsh Panikkar, Kersi H. Vakil, Pete D. Vogt
-
Publication number: 20080080654Abstract: In general, in one aspect, the disclosure describes an apparatus including a first deskew unit and a second deskew unit. The first deskew unit operates at a first clock domain and provides fine timing adjustment to a signal. The second deskew unit operates at a second clock domain that is slower than the first clock domain and provide coarse timing adjustment to the signal.Type: ApplicationFiled: September 29, 2006Publication date: April 3, 2008Inventors: Daniel S. Klowden, S. Reji Kumar, Adarsh Panikkar, Kersi H. Vakil, Abhimanyu Kolla
-
Patent number: 7346795Abstract: In some embodiments an apparatus and method may comprise a plurality of lanes between two clock domains, each lane comprising circuitry to generate a first signal when the lane may lose cycle coherency with other of the plurality of lanes, generate a second signal to signify a lane has been delayed, and a control circuit coupled with the plurality of lanes to add latency only to lanes that did not generate a second signal if the control circuit detects a first signal from any of the plurality of lanes.Type: GrantFiled: December 31, 2004Date of Patent: March 18, 2008Assignee: Intel CorporationInventors: Daniel S. Klowden, Adarsh Panikkar, S. Reji Kumar
-
Publication number: 20060149987Abstract: In some embodiments an apparatus and method may comprise a plurality of lanes between two clock domains, each lane comprising circuitry to generate a first signal when the lane may lose cycle coherency with other of the plurality of lanes, generate a second signal to signify a lane has been delayed, and a control circuit coupled with the plurality of lanes to add latency only to lanes that did not generate a second signal if the control circuit detects a first signal from any of the plurality of lanes.Type: ApplicationFiled: December 31, 2004Publication date: July 6, 2006Inventors: Daniel Klowden, Adarsh Panikkar, S. Kumar
-
Publication number: 20060146967Abstract: In some embodiments an apparatus may comprise a data circuit, a clock circuit to synchronize the data circuit; and a sampling circuit to sample a clock signal from a separate clock domain, the sampling circuit may control the clock circuit in response to the sampled clock signal and to delay the data circuit from providing data if it would result in data corruption due to clock misalignment.Type: ApplicationFiled: December 31, 2004Publication date: July 6, 2006Inventors: Adarsh Panikkar, Daniel Klowden, S. Kumar
-
Patent number: 7043392Abstract: According to some embodiments, a device includes an interpolator to receive at least a first clock signal having a first clock phase and to receive a second clock signal having a second clock phase. The interpolator may include a first plurality of interpolator legs associated with the first clock signal, a second plurality of interpolator legs associated with the second clock signal, and an output node to provide an output clock signal having an output clock phase based on the first clock signal, the second clock signal, and on a number of the first plurality and the second plurality of interpolator legs that are activated. The device may also include an interpolator control to activate only one of the first plurality and the second plurality of interpolator legs.Type: GrantFiled: June 16, 2004Date of Patent: May 9, 2006Assignee: Intel CorporationInventors: Kersi H. Vakil, Adarsh Panikkar, Abhimanyu Kolla, Arnaud Forestier
-
Publication number: 20060053328Abstract: Some embodiments of the invention provide a training sequence that may be used in a deskewing process or a protocol to be implemented in a training sequence deskew. Embodiments may also comprise a training pattern that allows for header or frame alignment.Type: ApplicationFiled: September 7, 2004Publication date: March 9, 2006Inventors: Adarsh Panikkar, S. Kumar, Daniel Klowden, Abhimanyu Kolla
-
Publication number: 20060050822Abstract: Some embodiments of the invention provide a biased tracking loop that may include encoded information. Embodiments may comprise a training pattern, utilized in a non-interfering way that allows for clock recovery, embedded information transmission and/or header alignment. Therefore, embodiments may comprise a tracking loop training pattern that comprises data.Type: ApplicationFiled: September 7, 2004Publication date: March 9, 2006Inventors: Adarsh Panikkar, Kersi Vakil, Pete Vogt
-
Patent number: 7009431Abstract: According to some embodiments, an interpolated clock signal having a first frequency is received, and the interpolated clock signal is periodically sampled based on a reference clock signal to generate periodically-sampled values, the reference clock signal having substantially the first frequency. A phase of the interpolated clock signal may be set to a phase degree at which the periodically-sampled values resolve to more than one value, and the phase of the interpolated clock signal may be incrementally changed until the periodically-sampled values resolve to one value. A non-linearity of the interpolated clock signal may be determined based on the number of incremental changes.Type: GrantFiled: June 29, 2004Date of Patent: March 7, 2006Assignee: Intel CorporationInventors: Adarsh Panikkar, Kersi H. Vakil, Abhimanyu Kolla, Arnaud Forestier
-
Publication number: 20050285652Abstract: According to some embodiments, an interpolated clock signal having a first frequency is received, and the interpolated clock signal is periodically sampled based on a reference clock signal to generate periodically-sampled values, the reference clock signal having substantially the first frequency. A phase of the interpolated clock signal may be set to a phase degree at which the periodically-sampled values resolve to more than one value, and the phase of the interpolated clock signal may be incrementally changed until the periodically-sampled values resolve to one value. A non-linearity of the interpolated clock signal may be determined based on the number of incremental changes.Type: ApplicationFiled: June 29, 2004Publication date: December 29, 2005Inventors: Adarsh Panikkar, Kersi Vakil, Abhimanyu Kolla, Arnaud Forestier
-
Publication number: 20050286565Abstract: Various methods, apparatuses and systems are described in which a skew delay time between communication lanes is determined. A data transfer path is established which includes two or more communication lanes in a communication link. A skew delay time is determined between the communication lanes of the communication link with respect each other with using a clock period of a input output circuit as a reference time.Type: ApplicationFiled: June 29, 2004Publication date: December 29, 2005Inventors: Kersi Vakil, Adarsh Panikkar
-
Publication number: 20050280452Abstract: According to some embodiments, a device includes an interpolator to receive at least a first clock signal having a first clock phase and to receive a second clock signal having a second clock phase. The interpolator may include a first plurality of interpolator legs associated with the first clock signal, a second plurality of interpolator legs associated with the second clock signal, and an output node to provide an output clock signal having an output clock phase based on the first clock signal, the second clock signal, and on a number of the first plurality and the second plurality of interpolator legs that are activated. The device may also include an interpolator control to activate only one of the first plurality and the second plurality of interpolator legs.Type: ApplicationFiled: June 16, 2004Publication date: December 22, 2005Inventors: Kersi Vakil, Adarsh Panikkar, Abhimanyu Kolla, Arnaud Forestier
-
Publication number: 20050129070Abstract: A method is described that involves loading X bits at a time into a shift register and shifting groups of older, loaded X bits up in the shift register with each new group of loaded X bits. Each group of X bits has been received from a serial data stream. The method further involves identifying an alignment key within the shift register and presenting aligned data from the serial data stream by rotating selection of a first group of Y contiguous bits from the shift register and a second group of Y contiguous bits from the shift register after the identifying. Y is greater than X.Type: ApplicationFiled: December 10, 2003Publication date: June 16, 2005Inventors: Adarsh Panikkar, Wayne Ashby, Abhimanyu Kolla