Patents by Inventor Addi Mistry

Addi Mistry has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080108179
    Abstract: A first packaged integrated circuit (IC) includes a package substrate, at least one IC die attached to a first surface of the package substrate, a plurality of conductive members on the first surface at least partially surrounding the at least one IC die and electrically connected to the at least one IC die, an encapsulant over the first surface surrounding the at least one IC die and the plurality of conductive members, wherein at least a portion of each of the plurality of conductive members is exposed by the encapsulant. A second packaged IC may be stacked onto the first packaged IC. The second packaged IC includes at least one IC die and a plurality of conductive members, each conductive member of the plurality of conductive members of the second packaged IC is in contact with a corresponding conductive member of the plurality conductive members of the first packaged IC.
    Type: Application
    Filed: January 3, 2008
    Publication date: May 8, 2008
    Applicant: Freescale Semiconductor, Inc
    Inventors: Addi Mistry, Marc Mangrum, David Patten, Jesse Phou, Ziep Tran
  • Publication number: 20070141751
    Abstract: A first packaged integrated circuit (IC) includes a package substrate, at least one IC die attached to a first surface of the package substrate, a plurality of conductive members on the first surface at least partially surrounding the at least one IC die and electrically connected to the at least one IC die, an encapsulant over the first surface surrounding the at least one IC die and the plurality of conductive members, wherein at least a portion of each of the plurality of conductive members is exposed by the encapsulant. A second packaged IC may be stacked onto the first packaged IC. The second packaged IC includes at least one IC die and a plurality of conductive members, each conductive member of the plurality of conductive members of the second packaged IC is in contact with a corresponding conductive member of the plurality conductive members of the first packaged IC.
    Type: Application
    Filed: December 16, 2005
    Publication date: June 21, 2007
    Inventors: Addi Mistry, Marc Mangrum, David Patten, Jesse Phou, Ziep Tran
  • Publication number: 20070096760
    Abstract: A method for testing a semiconductor structure having a set of top-side connections and having a set of bottom-side connections is provided. The method may include providing a device socket for connecting the set of top-side connections and the set of bottom-side connections to a tester. The method may further include providing a device hood for connecting the set of top-side connections to a respective first end of each of a plurality of interconnects in the device hood, wherein a second end of each of the plurality of interconnects in the device hood connects the set of top-side connections to the device socket. The method may further include testing the semiconductor structure using the tester. The semiconductor structure may include at least one integrated circuit to be tested.
    Type: Application
    Filed: October 31, 2005
    Publication date: May 3, 2007
    Inventors: Edmond Cheng, Addi Mistry, David Patten