Abstract: Devices, networks, systems, methods, and processes for determining receiver performance metric of a network device are described herein. A device may utilize one or more error patterns associated with the network device to retrieve one or more symbol errors from the one or more error patterns. The device can determine an error threshold for a segment based on a predefined Bit Error Rate (BER) level for the segment. The device may generate a performance metric for the segment based on the error threshold and the retrieved symbol errors. The device can generate a receiver performance metric based on performance metrics of segments. The device may determine a Code Error Ratio (CER) and can predict a Frame Loss ratio (FLR) associated with the network device based on the CER.

Abstract: Symbol multiplexing Physical Medium Attachment (PMA) may be provided. A plurality of first lanes may be received and then Alignment Markers (AMs) from the plurality of first lanes may be used to determine symbol boundaries and identify the plurality of first lanes. Next, groups of the plurality of first lanes may be de-skewed and checkerboard patterns in the plurality of first lanes may be undone. Then the plurality of first lanes may be symbol-wise multiplexed to a plurality of second lanes. The plurality of second lanes may then be sent.

Abstract: One embodiment provides a network device that includes PHY circuitry comprising transmit circuitry (Tx) and receive circuitry (Rx), wherein the Tx and Rx circuitry are configured to be coupled to a respective channel to communicate with an external device via the channels, wherein the network device configured to communicate with the external device using an Ethernet communications protocol; and test circuitry.

Abstract: One embodiment provides a network device that includes PHY circuitry comprising transmit circuitry (Tx) and receive circuitry (Rx), wherein the Tx and Rx circuitry are configured to be coupled to a respective channel to communicate with an external device via the channels, wherein the network device configured to communicate with the external device using an Ethernet communications protocol; and test circuitry.

Abstract: Techniques are described to adaptively adjust the equalizer settings of each transmitter in a transmitter-receiver pair. The transmitter-receiver pair can be used at least with implementations that comply with 40GBASE-CR4 or 100GBASE-CR10. For implementations that comply with 40GBASE-CR4, equalizer settings of four transmitters may be independently established.

Abstract: Techniques are described to adaptively adjust the equalizer settings of each transmitter in a transmitter-receiver pair. The transmitter-receiver pair can be used at least with implementations that comply with 40GBASE-CR4 or 100GBASE-CR10. For implementations that comply with 40GBASE-CR4, equalizer settings of four transmitters may be independently established.

Abstract: Techniques are described to adaptively adjust the equalizer settings of each transmitter in a transmitter-receiver pair. The transmitter-receiver pair can be used at least with implementations that comply with 40GBASE-CR4 or 100GBASE-CR10. For implementations that comply with 40GBASE-CR4, equalizer settings of four transmitters may be independently established.

Abstract: In one embodiment, the present invention includes an apparatus having an automatic gain control (AGC) stage to receive an input signal from a communication channel physical medium, a first local gain stage coupled to an output of the AGC stage, an equalizer coupled to an output of the first local gain stage, an echo canceller to receive local data to be transmitted along the communication channel physical medium, and a second local gain stage coupled to an output of the echo canceller. Other embodiments are described and claimed.

Abstract: A method and apparatus to improve adaptation speed of a digital receiver is presented. The receiver includes an equalizer to initiate adaptation to a transmission channel responsive to a first control signal, a slicer coupled to the equalizer to generate symbol decisions based at least in part on an equalized digital signal, logic to receive the symbol decisions and generate a selection signal when a lock onto a training sequence of the symbol decisions occurs, first and second phase detectors to detect phase errors of the equalized digital signal and an incoming digital signal, respectively, and a clock generator to generate a clock signal responsive to one of the first and second phase errors.

Abstract: In one embodiment, the present invention includes a method for receiving an incoming signal from a communication channel at a receiver, sampling the incoming signal in first and second samplers that are independently clocked, comparing outputs of the samplers, and outputting a measure of a horizontal eye opening of the incoming signal based on the comparison. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes an apparatus having a digital signal processor (DSP) coupled to receive a digitized signal. The DSP may be controlled to perform a timing recovery mechanism that implements a Mueller and Müller (MM)-based algorithm to generate a sensor output responsive to the digitized signal, where the incoming signal is non-linearly precoded in a transmitter from which the signal is received. Other embodiments are described and claimed.

Abstract: Techniques are described to adaptively adjust the equalizer settings of each transmitter in a transmitter-receiver pair. The transmitter-receiver pair can be used at least with implementations that comply with 40GBASE-CR4 or 100GBASE-CR10. For implementations that comply with 40GBASE-CR4, equalizer settings of four transmitters may be independently established.

Abstract: A method and apparatus to improve adaptation speed of a digital receiver is presented. The receiver includes an equalizer to initiate adaptation to a transmission channel responsive to a first control signal, a slicer coupled to the equalizer to generate symbol decisions based at least in part on an equalized digital signal, logic to receive the symbol decisions and generate a selection signal when a lock onto a training sequence of the symbol decisions occurs, first and second phase detectors to detect phase errors of the equalized digital signal and an incoming digital signal, respectively, and a clock generator to generate a clock signal responsive to one of the first and second phase errors.

Abstract: In one embodiment, the present invention includes an apparatus having a digital signal processor (DSP) coupled to receive a digitized signal. The DSP may be controlled to perform a timing recovery mechanism that implements a Mueller and Müller (MM)-based algorithm to generate a sensor output responsive to the digitized signal, where the incoming signal is non-linearly precoded in a transmitter from which the signal is received. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes an apparatus having an automatic gain control (AGC) stage to receive an input signal from a communication channel physical medium, a first local gain stage coupled to an output of the AGC stage, an equalizer coupled to an output of the first local gain stage, an echo canceler to receive local data to be transmitted along the communication channel physical medium, and a second local gain stage coupled to an output of the echo canceler. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for receiving an incoming signal from a communication channel at a receiver, sampling the incoming signal in first and second samplers that are independently clocked, comparing outputs of the samplers, and outputting a measure of a horizontal eye opening of the incoming signal based on the comparison. Other embodiments are described and claimed.

Abstract: Apparatus and systems, as well as methods and articles, may operate to receive a data signal from a transmitter at a selected channel included in a plurality of receiver channels, derive clock frequency deviation information from the data signal, receive an operational mode indication, and communicate the clock frequency deviation information to a remainder of the plurality of receiver channels responsive to receiving the operational mode indication, which may include a slave mode indication, a master mode indication, a full-duplex mode indication, or a half-duplex mode indication.