Patents by Inventor Adel El Sayed

Adel El Sayed has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250336493
    Abstract: A method for empowering a user, comprising the steps of establishing a plurality of pre-determined goals, storing a plurality of milestones related to each of the plurality of predetermined goals, having a user announce a stated goal, and determining whether the stated goal comprises one of the plurality of pre-determined goals. If the stated goal comprises one of the plurality of pre-determined goals, using the previously stored milestones. If the stated goal does not comprise one of the plurality of pre-determined goals, having the user establish a customized goal. If establishing a customized goal, the method comprises the steps of developing a plurality of customized milestones and developing a plurality of customized sub-milestones. The method further comprising the steps of having the user state a date of accomplishment and having the user state an affirmation statement.
    Type: Application
    Filed: April 28, 2024
    Publication date: October 30, 2025
    Inventors: Emadeldin El Sayed, Adel El Sayed
  • Patent number: 7323409
    Abstract: A multilevel metal and via structure is described. The metal conductors include a base or seed layer, a bulk conductor layer, a capping layer, and a barrier layer, and the via structure include a seed layer, a diffusion barrier layer and a metal plug. The via seed layer is controlled to a thickness that discourages the reaction between the via seed layer and the bulk conductor layer. The reaction may result in the formation of harmful voids at the bottom of the vias and is caused by having the via seed metal coming in contact with the bulk conductor through openings in the barrier layer.
    Type: Grant
    Filed: February 7, 2005
    Date of Patent: January 29, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Alfred J. Griffin, Jr., Adel El Sayed, John P. Campbell, Clint L. Montgomery
  • Patent number: 6977437
    Abstract: A multilevel metal and via structure is described. The metal conductors include a base or seed layer, a bulk conductor layer, a capping layer, and a barrier layer, and the via structure include a seed layer, a diffusion barrier layer and a metal plug. The via seed layer is controlled to a thickness that discourages the reaction between the via seed layer and the bulk conductor layer. The reaction may result in the formation of harmful voids at the bottom of the vias and is caused by having the via seed metal coming in contact with the bulk conductor through openings in the barrier layer.
    Type: Grant
    Filed: March 11, 2003
    Date of Patent: December 20, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Alfred J. Griffin, Jr., Adel El Sayed, John P. Campbell, Clint L. Montgomery
  • Publication number: 20050146035
    Abstract: A multilevel metal and via structure is described. The metal conductors include a base or seed layer, a bulk conductor layer, a capping layer, and a barrier layer, and the via structure include a seed layer, a diffusion barrier layer and a metal plug. The via seed layer is controlled to a thickness that discourages the reaction between the via seed layer and the bulk conductor layer. The reaction may result in the formation of harmful voids at the bottom of the vias and is caused by having the via seed metal coming in contact with the bulk conductor through openings in the barrier layer.
    Type: Application
    Filed: February 7, 2005
    Publication date: July 7, 2005
    Inventors: Alfred Griffin, Adel El Sayed, John Campbell, Clint Montgomery
  • Publication number: 20040178504
    Abstract: A multilevel metal and via structure is described. The metal conductors include a base or seed layer, a bulk conductor layer, a capping layer, and a barrier layer, and the via structure include a seed layer, a diffusion barrier layer and a metal plug.
    Type: Application
    Filed: March 11, 2003
    Publication date: September 16, 2004
    Inventors: Alfred J. Griffin, Adel El Sayed, John P. Campbell, Clint L. Montgomery
  • Publication number: 20030190801
    Abstract: A process whereby elimination of metal extrusion through the via-barrier layer into the base of etched via holes is accomplished by controlling the process temperature of the via-barrier deposition to less than 400° C., and preferably to about 380° C. By eliminating the cause of metal extrusions, i.e., excessive thermally induced stresses on the metal confined biaxially by the dielectric via walls, the resulting defect-free vias are independent of the barrier thickness. The method is applicable to different metal stacks, and in turn, yield and reliability of the device is significantly enhanced.
    Type: Application
    Filed: April 1, 2003
    Publication date: October 9, 2003
    Inventors: Alfred J. Griffin, Antonietta Oliva, Adel El Sayed
  • Publication number: 20030170975
    Abstract: A process whereby elimination of metal extrusion through the via-barrier layer into the base of etched via holes is accomplished by controlling the process temperature of the via-barrier deposition to less than 400° C., and preferably to about 380° C. By eliminating the cause of metal extrusions, i.e., excessive thermally induced stresses on the metal confined biaxially by the dielectric via walls, the resulting defect-free vias are independent of the barrier thickness. The method is applicable to different metal stacks, and in turn, yield and reliability of the device is significantly enhanced.
    Type: Application
    Filed: March 6, 2002
    Publication date: September 11, 2003
    Inventors: Alfred J. Griffin, Antonietta Oliva, Adel El Sayed
  • Patent number: 6617231
    Abstract: A process whereby elimination of metal extrusion through the via-barrier layer into the base of etched via holes is accomplished by controlling the process temperature of the via-barrier deposition to less than 400° C., and preferably to about 380° C. By eliminating the cause of metal extrusions, i.e., excessive thermally induced stresses on the metal confined biaxially by the dielectric via walls, the resulting defect-free vias are independent of the barrier thickness. The method is applicable to different metal stacks, and in turn, yield and reliability of the device is significantly enhanced.
    Type: Grant
    Filed: March 6, 2002
    Date of Patent: September 9, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Alfred J. Griffin, Jr., Antonietta Oliva, Adel El Sayed