Patents by Inventor Adel Elsherbini

Adel Elsherbini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11990419
    Abstract: Techniques and mechanisms for providing physically unclonable function (PUF) circuitry at a substrate which supports coupling to an integrated circuit (IC) chip. In an embodiment, the substrate comprises an array of electrodes which extend in a level of metallization at a side of the insulator layer. A cap layer, disposed on the array, is in contact with the electrodes and with a portion of the insulator layer which is between the electrodes. A material of the cap layer has a different composition or microstructure than the metallization. Regions of the cap layer variously provide respective impedances each between a corresponding two electrodes. In other embodiments, the substrate includes (or couples to) integrated circuitry that is operable to determine security information based on the detection of one or more such impedances.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: May 21, 2024
    Assignee: Intel Corporation
    Inventors: Georgios Dogiamis, Feras Eid, Adel Elsherbini, David Johnston, Jyothi Bhaskarr Velamala, Rachael Parker
  • Patent number: 11990448
    Abstract: Disclosed herein are microelectronic assemblies including direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first subregion and a second subregion, and the first subregion has a greater metal density than the second subregion. In some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first metal contact and a second metal contact, the first metal contact has a larger area than the second metal contact, and the first metal contact is electrically coupled to a power/ground plane of the first microelectronic component.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: May 21, 2024
    Assignee: Intel Corporation
    Inventors: Feras Eid, Adel A. Elsherbini, Aleksandar Aleksov, Shawna M. Liff, Johanna M. Swan
  • Patent number: 11984439
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface, wherein the first die is embedded in a first dielectric layer, wherein the first surface of the first die is coupled to the second surface of the package substrate, and wherein the first dielectric layer is between a second dielectric layer and the second surface of the package substrate; a second die having a first surface and an opposing second surface, wherein the second die is embedded in the second dielectric layer, and wherein the first surface of the second die is coupled to the second surface of the package substrate by a conductive pillar; and a shield structure that at least partially surrounds the conductive pillar.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: May 14, 2024
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Georgios Dogiamis, Shawna M. Liff, Zhiguo Qian, Johanna M. Swan
  • Publication number: 20240136323
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.
    Type: Application
    Filed: January 3, 2024
    Publication date: April 25, 2024
    Applicant: Intel Corporation
    Inventors: Shawna M. Liff, Adel A. Elsherbini, Johanna M. Swan, Arun Chandrasekhar
  • Patent number: 11967580
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: April 23, 2024
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Amr Elshazly, Arun Chandrasekhar, Shawna M. Liff, Johanna M. Swan
  • Publication number: 20240128255
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.
    Type: Application
    Filed: December 27, 2023
    Publication date: April 18, 2024
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, Shawna M. Liff, Johanna M. Swan, Arun Chandrasekhar
  • Publication number: 20240113052
    Abstract: In various embodiments, disclosed herein are systems and methods directed to the fabrication of a coreless semiconductor package (e.g., a millimeter (mm)-wave antenna package) having an asymmetric build-up layer count that can be fabricated on both sides of a temporary substrate (e.g., a core). The asymmetric build-up layer count can reduce the overall layer count in the fabrication of the semiconductor package and can therefore contribute to fabrication cost reduction. In further embodiments, the semiconductor package (e.g., a millimeter (mm)-wave antenna packages) can further comprise dummification elements disposed near one or more antenna layers. Further, the dummification elements disposed near one or more antenna layers can reduce image current and thereby increasing the antenna gain and efficiency.
    Type: Application
    Filed: December 15, 2023
    Publication date: April 4, 2024
    Inventors: Telesphor Kamgaing, Adel A. Elsherbini, Sasha Oster
  • Patent number: 11933555
    Abstract: A heat dissipation device may be formed having at least one isotropic thermally conductive section (uniformly high thermal conductivity in all directions) and at least one anisotropic thermally conductive section (high thermal conductivity in at least one direction and low thermal conductivity in at least one other direction). The heat dissipation device may be thermally coupled to a plurality of integrated circuit devices such that at least a portion of the isotropic thermally conductive section(s) and/or the anisotropic thermally conductive section(s) is positioned over at least one integrated circuit device.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: March 19, 2024
    Assignee: Intel Corporation
    Inventors: Feras Eid, Adel Elsherbini, Johanna Swan
  • Patent number: 11916020
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: February 27, 2024
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Amr Elshazly, Arun Chandrasekhar, Shawna M. Liff, Johanna M. Swan
  • Patent number: 11916006
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a first surface and an opposing second surface; and a chiplet having a first surface and an opposing second surface, wherein the chiplet is between the surface of the package substrate and the first surface of the die, wherein the first surface of the chiplet is coupled to the surface of the package substrate and the second surface of the chiplet is coupled to the first surface of the die, and wherein the chiplet includes: a capacitor at the first surface; and an element at the second surface, wherein the element includes a switching transistor or a diode.
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: February 27, 2024
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Kaladhar Radhakrishnan, Krishna Bharath, Shawna M. Liff, Johanna M. Swan
  • Publication number: 20240063179
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a dielectric layer having one or more conductive traces and a surface; a microelectronic subassembly on the surface of the dielectric layer, the microelectronic subassembly including a first die and a through-dielectric via (TDV) surrounded by a dielectric material, wherein the first die is at the surface of the dielectric layer; a second die and a third die on the first die and electrically coupled to the first die by interconnects having a pitch of less than 10 microns, and wherein the TDV is electrically coupled at a first end to the dielectric layer and at an opposing second end to the second die; and a substrate on and coupled to the second and third dies; and an insulating material on the surface of the dielectric layer and around the microelectronic subassembly.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, Krishna Vasanth Valavala, Kimin Jun, Shawna M. Liff, Johanna M. Swan, Debendra Mallik, Feras Eid, Xavier Francois Brun, Bhaskar Jyoti Krishnatreya
  • Publication number: 20240063076
    Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more integrated circuit dies bonded to a base die, a conformal thermal heat spreading layer on the top and sidewalls of the integrated circuit dies, and an inorganic dielectric material on a portion of the conformal thermal heat spreading layer, laterally adjacent the integrated circuit dies, and over the base die. The conformal thermal heat spreading layer includes a high thermal conductivity material to provide a thermal pathway for the integrated circuit dies during operation.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Applicant: Intel Corporation
    Inventors: Mohammad Enamul Kabir, Bhaskar Jyoti Krishnatreya, Kimin Jun, Adel Elsherbini, Tushar Talukdar, Feras Eid, Debendra Mallik, Krishna Vasanth Valavala, Xavier Brun
  • Publication number: 20240063133
    Abstract: A multichip composite device includes on- and off-die metallization layers, inorganic dielectric material, and stacked hybrid-bonded dies. On-die metallization layers may be thinner than off-die metallization layers. The multichip composite device may include a structural substrate. Off-die metallization layers may be above and below the stacked hybrid-bonded dies. A substrate may couple the multichip composite device to a power supply in a multichip system. Forming a multichip composite device includes hybrid bonding dies and forming inorganic dielectric material.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Applicant: Intel Corporation
    Inventors: Adel Elsherbini, Beomseok Choi, Feras Eid, Omkar Karhade, Shawna Liff
  • Publication number: 20240063178
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die and a through-dielectric via (TDV) surrounded by a dielectric material in a first layer, where the TDV has a greater width at a first surface and a smaller width at an opposing second surface of the first layer; a second die, surrounded by the dielectric material, in a second layer on the first layer, where the first die is coupled to the second die by interconnects having a pitch of less than 10 microns, and the dielectric material around the second die has an interface seam extending from a second surface of the second layer towards an opposing first surface of the second layer with an angle of less than 90 degrees relative to the second surface; and a substrate on and coupled to the second layer.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Applicant: Intel Corporation
    Inventors: Jimin Yao, Adel A. Elsherbini, Xavier Francois Brun, Kimin Jun, Shawna M. Liff, Johanna M. Swan, Yi Shi, Tushar Talukdar, Feras Eid, Mohammad Enamul Kabir, Omkar G. Karhade, Bhaskar Jyoti Krishnatreya
  • Publication number: 20240063180
    Abstract: Quasi-monolithic multi-die composites including a primary fill structure within a space between adjacent IC dies. A fill material layer, which may have inorganic composition, may be bonded to a host substrate and patterned to form a primary fill structure that occupies a first portion of the host substrate. IC dies may be bonded to regions of the host substrate within openings where the primary fill structure is absent to have a spatial arrangement complementary to the primary fill structure. The primary fill structure may have a thickness substantially matching that of IC dies and/or be co-planar with a surface of one or more of the IC dies. A gap fill material may then be deposited within remnants of the openings to form a secondary fill structure that occupies space between the IC dies and the primary fill structure.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Applicant: Intel Corporation
    Inventors: Kimin Jun, Adel Elsherbini, Omkar Karhade, Bhaskar Jyoti Krishnatreya, Mohammad Enamul Kabir, Jiraporn Seangatith, Tushar Talukdar, Shawna Liff, Johanna Swan, Feras Eid
  • Publication number: 20240063202
    Abstract: Embodiments of a microelectronic assembly comprise: a plurality of layers of IC dies in a dielectric material, adjacent layers in the plurality of layers being coupled together by first interconnects having a pitch of less than 10 micrometers between adjacent first interconnects; a package substrate coupled to a first side of the plurality of layers by second interconnects; a support structure coupled to a second side of the plurality of layers by third interconnects, the second side being opposite to the first side; and capacitors in at least the plurality of layers or the support structure. The capacitors are selected from at least planar capacitors, deep trench capacitors and via capacitors.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, Thomas Sounart, Henning Braunisch, William J. Lambert, Kaladhar Radhakrishnan, Shawna M. Liff, Mohammad Enamul Kabir, Omkar G. Karhade, Kimin Jun, Johanna M. Swan
  • Publication number: 20240063120
    Abstract: Embodiments of a microelectronic assembly comprise: a plurality of layers of integrated circuit (IC) dies, each layer coupled to adjacent layers by first interconnects having a pitch of less than 10 micrometers between adjacent first interconnects; an end layer in the plurality of layers proximate to a first side of the plurality of layers comprises a dielectric material around IC dies in the end layer and a through-dielectric via (TDV) in the dielectric material of the end layer; a support structure coupled to the first side of the plurality of layers, the support structure comprising a structurally stiff base with conductive traces proximate to the end layer, the conductive traces coupled to the end layer by second interconnects; and a package substrate coupled to a second side of the plurality of layers, the second side being opposite to the first side.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, Shawna M. Liff, Debendra Mallik, Christopher M. Pelto, Kimin Jun, Johanna M. Swan, Lei Jiang, Feras Eid, Krishna Vasanth Valavala, Henning Braunisch, Patrick Morrow, William J. Lambert
  • Publication number: 20240063089
    Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more integrated circuit dies bonded to a base die and an inorganic dielectric material adjacent the integrated circuit dies and over the base die. The multichip composite device includes a dummy die, dummy vias, or integrated fluidic cooling channels laterally adjacent the integrated circuit dies to conduct heat from the base die.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Applicant: Intel Corporation
    Inventors: Adel Elsherbini, Wenhao Li, Bhaskar Jyoti Krishnatreya, Debendra Mallik, Krishna Vasanth Valavala, Lei Jiang, Yoshihiro Tomita, Omkar Karhade, Haris Khan Niazi, Tushar Talukdar, Mohammad Enamul Kabir, Xavier Brun, Feras Eid
  • Publication number: 20240063072
    Abstract: Composite integrated circuit (IC) device processing, including selective removal of inorganic dielectric material. Inorganic dielectric material may be deposited, modified with laser exposure, and selectively removed. Laser exposure parameters may be adjusted using surface topography measurements. Inorganic dielectric material removal may reduce surface topography. Vias and trenches of varying size, shape, and depth may be concurrently formed without an etch-stop layer. A composite IC device may include an IC die, a conductive via, and a conductive line adjacent a compositionally homogenous inorganic dielectric material.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Applicant: Intel Corporation
    Inventors: Adel Elsherbini, Shawna Liff, Kimin Jun, Veronica Strong, Aleksandar Aleksov, Jiraporn Seangatith, Mohammad Enamul Kabir, Johanna Swan, Tushar Talukdar, Omkar Karhade
  • Publication number: 20240063142
    Abstract: Multi-die packages including IC die crack mitigation features. Prior to the bonding of IC dies to a host substrate, the IC dies may be shaped, for example with a corner radius or chamfer. After bonding the shaped IC dies, a fill comprising at least one inorganic material may be deposited over the IC dies, for example to backfill a space between adjacent IC dies. With the benefit of a greater IC die sidewall slope and/or smoother surface topology associated with the shaping process, occurrences of stress cracking within the fill and concomitant damage to the IC dies may be reduced. Prior to depositing a fill, a barrier layer may be deposited over the IC die to prevent cracks that might form in the fill material from propagating into the IC die.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Applicant: Intel Corporation
    Inventors: Adel Elsherbini, Wenhao Li, Bhaskar Jyoti Krishnatreya, Tushar Talukdar, Botao Zhang, Yi Shi, Haris Khan Niazi, Feras Eid, Nagatoshi Tsunoda, Xavier Brun, Mohammad Enamul Kabir, Omkar Karhade, Shawna Liff, Jiraporn Seangatith