Patents by Inventor Adel Elsherbini
Adel Elsherbini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12040307Abstract: Magnetic structures incorporated into integrated circuit assemblies. In some examples, the magnetic structures may enable local heating and reflow of solder interconnects for the attachment of integrated circuit devices to electronic substrates.Type: GrantFiled: May 29, 2020Date of Patent: July 16, 2024Assignee: Intel CorporationInventors: Feras Eid, Adel Elsherbini, Georgios Dogiamis
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Publication number: 20240213216Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.Type: ApplicationFiled: March 6, 2024Publication date: June 27, 2024Inventors: Adel A. ELSHERBINI, Amr Elshazly, Arun CHANDRASEKHAR, Shawna M. LIFF, Johanna M. SWAN
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Patent number: 12014990Abstract: Techniques and mechanisms for high interconnect density communication with an interposer. In some embodiments, an interposer comprises a substrate and portions disposed thereon, wherein respective inorganic dielectrics of said portions adjoin each other at a material interface, which extends to each of the substrate and a first side of the interposer. A first hardware interface of the interposer spans the material interface at the first side, wherein a first one of said portions comprises first interconnects which couple the first hardware interface to a second hardware interface at the first side. A second one of said portions includes second interconnects which couple one of first hardware interface or the second hardware interface to a third hardware interface at another side of the interposer. In another embodiment, a metallization pitch feature of the first hardware interface is smaller than a corresponding metallization pitch feature of the second hardware interface.Type: GrantFiled: April 10, 2023Date of Patent: June 18, 2024Assignee: Intel CorporationInventors: Adel Elsherbini, Shawna Liff, Johanna Swan, Gerald Pasdast
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Patent number: 12002745Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.Type: GrantFiled: December 7, 2021Date of Patent: June 4, 2024Assignee: Intel CorporationInventors: Adel A. Elsherbini, Mathew J. Manusharow, Krishna Bharath, William J. Lambert, Robert L. Sankman, Aleksandar Aleksov, Brandon M. Rawlings, Feras Eid, Javier Soto Gonzalez, Meizi Jiao, Suddhasattwa Nad, Telesphor Kamgaing
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Patent number: 11990448Abstract: Disclosed herein are microelectronic assemblies including direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first subregion and a second subregion, and the first subregion has a greater metal density than the second subregion. In some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first metal contact and a second metal contact, the first metal contact has a larger area than the second metal contact, and the first metal contact is electrically coupled to a power/ground plane of the first microelectronic component.Type: GrantFiled: September 18, 2020Date of Patent: May 21, 2024Assignee: Intel CorporationInventors: Feras Eid, Adel A. Elsherbini, Aleksandar Aleksov, Shawna M. Liff, Johanna M. Swan
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Patent number: 11990419Abstract: Techniques and mechanisms for providing physically unclonable function (PUF) circuitry at a substrate which supports coupling to an integrated circuit (IC) chip. In an embodiment, the substrate comprises an array of electrodes which extend in a level of metallization at a side of the insulator layer. A cap layer, disposed on the array, is in contact with the electrodes and with a portion of the insulator layer which is between the electrodes. A material of the cap layer has a different composition or microstructure than the metallization. Regions of the cap layer variously provide respective impedances each between a corresponding two electrodes. In other embodiments, the substrate includes (or couples to) integrated circuitry that is operable to determine security information based on the detection of one or more such impedances.Type: GrantFiled: June 18, 2020Date of Patent: May 21, 2024Assignee: Intel CorporationInventors: Georgios Dogiamis, Feras Eid, Adel Elsherbini, David Johnston, Jyothi Bhaskarr Velamala, Rachael Parker
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Patent number: 11984439Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface, wherein the first die is embedded in a first dielectric layer, wherein the first surface of the first die is coupled to the second surface of the package substrate, and wherein the first dielectric layer is between a second dielectric layer and the second surface of the package substrate; a second die having a first surface and an opposing second surface, wherein the second die is embedded in the second dielectric layer, and wherein the first surface of the second die is coupled to the second surface of the package substrate by a conductive pillar; and a shield structure that at least partially surrounds the conductive pillar.Type: GrantFiled: October 16, 2018Date of Patent: May 14, 2024Assignee: Intel CorporationInventors: Adel A. Elsherbini, Georgios Dogiamis, Shawna M. Liff, Zhiguo Qian, Johanna M. Swan
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Publication number: 20240136323Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.Type: ApplicationFiled: January 3, 2024Publication date: April 25, 2024Applicant: Intel CorporationInventors: Shawna M. Liff, Adel A. Elsherbini, Johanna M. Swan, Arun Chandrasekhar
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Patent number: 11967580Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.Type: GrantFiled: September 29, 2022Date of Patent: April 23, 2024Assignee: Intel CorporationInventors: Adel A. Elsherbini, Amr Elshazly, Arun Chandrasekhar, Shawna M. Liff, Johanna M. Swan
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Publication number: 20240128255Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.Type: ApplicationFiled: December 27, 2023Publication date: April 18, 2024Applicant: Intel CorporationInventors: Adel A. Elsherbini, Shawna M. Liff, Johanna M. Swan, Arun Chandrasekhar
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Publication number: 20240113052Abstract: In various embodiments, disclosed herein are systems and methods directed to the fabrication of a coreless semiconductor package (e.g., a millimeter (mm)-wave antenna package) having an asymmetric build-up layer count that can be fabricated on both sides of a temporary substrate (e.g., a core). The asymmetric build-up layer count can reduce the overall layer count in the fabrication of the semiconductor package and can therefore contribute to fabrication cost reduction. In further embodiments, the semiconductor package (e.g., a millimeter (mm)-wave antenna packages) can further comprise dummification elements disposed near one or more antenna layers. Further, the dummification elements disposed near one or more antenna layers can reduce image current and thereby increasing the antenna gain and efficiency.Type: ApplicationFiled: December 15, 2023Publication date: April 4, 2024Inventors: Telesphor Kamgaing, Adel A. Elsherbini, Sasha Oster
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Patent number: 11933555Abstract: A heat dissipation device may be formed having at least one isotropic thermally conductive section (uniformly high thermal conductivity in all directions) and at least one anisotropic thermally conductive section (high thermal conductivity in at least one direction and low thermal conductivity in at least one other direction). The heat dissipation device may be thermally coupled to a plurality of integrated circuit devices such that at least a portion of the isotropic thermally conductive section(s) and/or the anisotropic thermally conductive section(s) is positioned over at least one integrated circuit device.Type: GrantFiled: October 25, 2021Date of Patent: March 19, 2024Assignee: Intel CorporationInventors: Feras Eid, Adel Elsherbini, Johanna Swan
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Patent number: 11916006Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a first surface and an opposing second surface; and a chiplet having a first surface and an opposing second surface, wherein the chiplet is between the surface of the package substrate and the first surface of the die, wherein the first surface of the chiplet is coupled to the surface of the package substrate and the second surface of the chiplet is coupled to the first surface of the die, and wherein the chiplet includes: a capacitor at the first surface; and an element at the second surface, wherein the element includes a switching transistor or a diode.Type: GrantFiled: August 25, 2022Date of Patent: February 27, 2024Assignee: Intel CorporationInventors: Adel A. Elsherbini, Kaladhar Radhakrishnan, Krishna Bharath, Shawna M. Liff, Johanna M. Swan
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Patent number: 11916020Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.Type: GrantFiled: October 29, 2021Date of Patent: February 27, 2024Assignee: Intel CorporationInventors: Adel A. Elsherbini, Amr Elshazly, Arun Chandrasekhar, Shawna M. Liff, Johanna M. Swan
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Publication number: 20240063120Abstract: Embodiments of a microelectronic assembly comprise: a plurality of layers of integrated circuit (IC) dies, each layer coupled to adjacent layers by first interconnects having a pitch of less than 10 micrometers between adjacent first interconnects; an end layer in the plurality of layers proximate to a first side of the plurality of layers comprises a dielectric material around IC dies in the end layer and a through-dielectric via (TDV) in the dielectric material of the end layer; a support structure coupled to the first side of the plurality of layers, the support structure comprising a structurally stiff base with conductive traces proximate to the end layer, the conductive traces coupled to the end layer by second interconnects; and a package substrate coupled to a second side of the plurality of layers, the second side being opposite to the first side.Type: ApplicationFiled: August 19, 2022Publication date: February 22, 2024Applicant: Intel CorporationInventors: Adel A. Elsherbini, Shawna M. Liff, Debendra Mallik, Christopher M. Pelto, Kimin Jun, Johanna M. Swan, Lei Jiang, Feras Eid, Krishna Vasanth Valavala, Henning Braunisch, Patrick Morrow, William J. Lambert
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Publication number: 20240063142Abstract: Multi-die packages including IC die crack mitigation features. Prior to the bonding of IC dies to a host substrate, the IC dies may be shaped, for example with a corner radius or chamfer. After bonding the shaped IC dies, a fill comprising at least one inorganic material may be deposited over the IC dies, for example to backfill a space between adjacent IC dies. With the benefit of a greater IC die sidewall slope and/or smoother surface topology associated with the shaping process, occurrences of stress cracking within the fill and concomitant damage to the IC dies may be reduced. Prior to depositing a fill, a barrier layer may be deposited over the IC die to prevent cracks that might form in the fill material from propagating into the IC die.Type: ApplicationFiled: August 19, 2022Publication date: February 22, 2024Applicant: Intel CorporationInventors: Adel Elsherbini, Wenhao Li, Bhaskar Jyoti Krishnatreya, Tushar Talukdar, Botao Zhang, Yi Shi, Haris Khan Niazi, Feras Eid, Nagatoshi Tsunoda, Xavier Brun, Mohammad Enamul Kabir, Omkar Karhade, Shawna Liff, Jiraporn Seangatith
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Publication number: 20240063183Abstract: Embodiments of a microelectronic assembly comprise: a plurality of layers of monolithic wafers and disaggregated integrated circuit (IC) dies, adjacent layers being coupled together by first interconnects having a pitch less than 10 micrometers between adjacent first interconnects, the disaggregated IC dies arranged with portions of the monolithic wafers into modular sub-assemblies; and a package substrate coupled to the modular sub-assemblies by second interconnects having a pitch greater than 10 micrometers between adjacent second interconnects. The disaggregated IC dies are surrounded laterally by a dielectric material, and the disaggregated IC dies are arranged with portions of the monolithic wafers such that a voltage regulator circuit in a first layer of the plurality of layers, a compute circuit in a second layer of the plurality of layers, and a memory circuit in a third layer of the plurality of layers are conductively coupled together in an intra-modular power delivery circuitry.Type: ApplicationFiled: August 19, 2022Publication date: February 22, 2024Applicant: Intel CorporationInventors: Adel A. Elsherbini, Kaladhar Radhakrishnan, Anne Augustine, Beomseok Choi, Kimin Jun, Omkar G. Karhade, Shawna M. Liff, Julien Sebot, Johanna M. Swan, Krishna Vasanth Valavala
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Publication number: 20240063071Abstract: Multi-die composite structures including a multi-layered inorganic dielectric gap fill material within a space between adjacent IC dies. A first layer of fill material with an inorganic composition may be deposited over IC dies with a high-rate deposition process, for example to at least partially fill a space between the IC dies. The first layer of fill material may then be partially removed to modify a sidewall slope of the first layer or otherwise reduce an aspect ratio of the space between the IC dies. Another layer of fill material may be deposited over the lower layer of fill material, for example with the same high-rate deposition process. This dep-etch-dep cycle may be repeated any number of times to backfill spaces between IC dies. The multi-layer fill material may then be globally planarized and the IC die package completed and/or assembled into a next-level of integration.Type: ApplicationFiled: August 19, 2022Publication date: February 22, 2024Applicant: Intel CorporationInventors: Jeffery Bielefeld, Adel Elsherbini, Bhaskar Jyoti Krishnatreya, Feras Eid, Gauri Auluck, Kimin Jun, Mohammad Enamul Kabir, Nagatoshi Tsunoda, Renata Camillo-Castillo, Tristan A. Tronic, Xavier Brun
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Publication number: 20240063076Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more integrated circuit dies bonded to a base die, a conformal thermal heat spreading layer on the top and sidewalls of the integrated circuit dies, and an inorganic dielectric material on a portion of the conformal thermal heat spreading layer, laterally adjacent the integrated circuit dies, and over the base die. The conformal thermal heat spreading layer includes a high thermal conductivity material to provide a thermal pathway for the integrated circuit dies during operation.Type: ApplicationFiled: August 19, 2022Publication date: February 22, 2024Applicant: Intel CorporationInventors: Mohammad Enamul Kabir, Bhaskar Jyoti Krishnatreya, Kimin Jun, Adel Elsherbini, Tushar Talukdar, Feras Eid, Debendra Mallik, Krishna Vasanth Valavala, Xavier Brun
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Publication number: 20240063066Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die having a surface; a template structure having a first surface and an opposing second surface, wherein the first surface of the template structure is coupled to the surface of the first die, and wherein the template structure includes a cavity at the first surface and a through-template opening extending from a top surface of the cavity to the second surface of the template structure; and a second die within the cavity of the template structure and electrically coupled to the surface of the first die by interconnects having a pitch of less than 10 microns between adjacent interconnects.Type: ApplicationFiled: August 19, 2022Publication date: February 22, 2024Applicant: Intel CorporationInventors: Omkar G. Karhade, Tomita Yoshihiro, Adel A. Elsherbini, Bhaskar Jyoti Krishnatreya, Tushar Talukdar, Haris Khan Niazi, Yi Shi, Batao Zhang, Wenhao Li, Feras Eid