Abstract: Systems, methods and apparatus are provided for transistors having a first source/drain region, a second source/drain region, and a channel region, wherein the channel region comprises an antimony-gallium-zinc-oxide (SbGZO) material.

Abstract: Memory circuitry comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a capacitor and a horizontally-oriented transistor. Semiconductor material is directly below the vertically-alternating tiers. Insulative vertical walls extend through the vertically-alternating tiers into the semiconductor material there-below. Individual of the insulative vertical walls below a top of the semiconductor material comprise an upper portion directly above and joined with a lower portion. The individual insulative vertical walls comprise at least one external jog surface in a vertical cross-section in and below the top of the semiconductor material where the upper and lower portions join. The lower portion is wider in the vertical cross-section in the semiconductor material than the upper portion where the upper and lower portions join in the semiconductor material. Method embodiments are disclosed.

Abstract: Systems, methods and apparatus are provided for transistors having a channel region comprising a crystalline spinel indium-gallium-zinc-oxide (IGZO) material.

Abstract: Systems, methods and apparatus are provided for transistors having a first source/drain region, a second source/drain region, and a channel region, wherein the channel region comprises an antimony-gallium-zinc-oxide (SbGZO) material.