Abstract: The present disclosure describes techniques for hardware acceleration for routing programs. In some aspects communications between a routing determination program and a packet router are monitored in a router, both the routing determination program and the packet router being part of a software layer of the router. The communications include the routing determination program providing configuration data to the packet router. Based on the monitored communications, a packet processor is changed to reflect the configuration data, the packet processor being part of a hardware layer of the router. The packet processor performs packet routing operations of receiving packets, determining the next routers in the paths to the target destinations of the packets, and sending the packets to the next routers independent of the software layer.

Abstract: The present disclosure describes techniques for hardware acceleration for routing programs. In some aspects communications between a routing determination program and a packet router are monitored in a router, both the routing determination program and the packet router being part of a software layer of the router. The communications include the routing determination program providing configuration data to the packet router. Based on the monitored communications, a packet processor is changed to reflect the configuration data, the packet processor being part of a hardware layer of the router. The packet processor performs packet routing operations of receiving packets, determining the next routers in the paths to the target destinations of the packets, and sending the packets to the next routers independent of the software layer.

Abstract: A method and apparatus for performing atomic accesses in a data processing system (10). In one embodiment, a small number of control signals (e.g. 100-102; or 103-104; or 105-108 from FIG. 3 ) are used to provide information regarding the status of reservations between bus masters (e.g. 80), bus interfaces (e.g. 84, 86, and 92), and snoop logic (e.g. 82,88, and 90). Snoop logic (e.g. 40 in FIG. 2) is required if multiple bus masters (12 and 46) are used. The control signals allow atomic accesses to be performed in a multi-master data processing system (10), while minimizing the circuitry required to be built on-board each bus master integrated circuit processor (e.g. 152 in FIG. 3). The result is lower cost processors (152) which can operate in multi-processor systems, but which are optimized for use in single-processor systems.

Abstract: A master device (11) can access slave devices (12) either speculatively or non-speculatively. The slave devices (12) can be either non-hazardous devices or hazardous devices which exhibit status changes on reading. The master device (11) issues an access request including information as to whether the request is speculative or non-speculative, the slave device (12) then responds to the master device (11) with a negative acknowledgment that access is denied if the access request is speculative and the slave device (12) is hazardous. Otherwise, if the slave device (12) can deal with the request, a positive acknowledgment is sent. If the master device (11) receives a negative acknowledgment, it continues to reissue updated access requests until a positive acknowledgment is received.

Abstract: A bus protocol is provided for pipelined and/or split transaction buses (18,48) which have in-order data bus termination and which do not require data bus arbitration. The present invention solves the problem of matching the initial address request by a bus master (12, 13, 42) to the corresponding data response from a bus slave (14, 15, 44) when the bus (18, 48) used for master-slave communication is a split-transaction bus and/or a pipelined bus. Each bus master (12, 13, 42) and each bus slave (14, 15, 44) has a counter (30-33, 75-76) which is used to store a current pipe depth value (21, 51) from a central pipe counter (16, 72). A transaction start signal (20, 50) and a transaction end signal (22, 52) are used to selectively increment and decrement the counters (30-33, 75-76).