Abstract: A junction FET switching circuit and method in which the gate-source voltage of the switching FET is varied with changing temperature so as to maintain the FET channel resistance substantially constant over a selected temperature range. An offset is introduced to the gate-source voltage to permit adequate voltage variation over the temperature range.

Abstract: A base junction transistor inverter circuit will be driven into the saturation region if the drive current is large enough. In such circumstances, the collector voltage can go below the base voltage and approaches the emitter voltage. A circuit is provided to keep the transistor out of saturation and is comprised of a p-channel field effect transistor (JFET) connected between the base and collector of the junction transistor. The JFET is connected such that when the drive current increases and the junction transistor approaches saturation, the drive current is diverted through the JFET and into the substrate. The same clamp can be implemented by using a pnp junction transistor in combination with an n-channel JFET.

Abstract: In a three JFET switch, a first transistor when turned on is utilized to pass an input voltage to an output. The first transistor is turned on by a second and third transistor having their gates commoned with the first transistor to form a turn on circuit. In its idle state, when the switch is off, a drain circuit conducts through the third transistor, dissipating power. In order to reduce the size of the second and third transistors and hence the power dissipated while maintaining a fast switching speed a bipolar transistor and a fourth JFET are utilized to amplify the drain current of the third transistor for discharging the common gate capacitance of the switch. This allows the second and third transistors to be made small since their current need not be large for high speed switching. Furthermore, the bipolar transistor only turns on during the transition from the open to closed state of the switch and therefore its conduction does not contribute to the quiescent power consumption of the circuit.

Abstract: A circuit for cancelling the offset voltage of a signal amplifier includes a second amplifier and a third amplifier connected to the outputs of the signal amplifier and the second amplifier. A capacitor is connected between the inputs of the second amplifier for storing the offset voltages of the amplifiers thereon. A switch connects the output of the third amplifier to the capacitor and a switch connects the inputs of the signal amplifier together during offset correction. When the offset voltages are stored on the capacitor, the switches open to permit signal amplification and cancellation of the offset voltages. In a second embodiment, a second capacitor stores the instantaneous amplitude of the signal being amplified and supplies it to an input of the second amplifier such that a discontinuity will not appear in the circuit output during offset correction.