Patents by Inventor Adil Bhanji

Adil Bhanji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240330551
    Abstract: Timing analysis of a digital integrated circuit using intent based timing constraints includes defining a plurality of intent groups for an integrated circuit design. Each intent group is associated with a different clock type of the integrated circuit design. A different timing phase of a plurality of timing phases of one or more clock signals of the integrated circuit design is associated with each intent group. One or more timing constraints is associated with each of the intent groups. A timing result is computed based on propagating the timing phases of each of the intent groups and applying the associated timing constraints from an input to a timing point of the integrated circuit design.
    Type: Application
    Filed: March 30, 2023
    Publication date: October 3, 2024
    Inventors: HEMLATA GUPTA, KERIM KALAFALA, MANISH VERMA, JENNIFER ELIZABETH BASILE, ADIL BHANJI, ERIC FOREMAN, JACK DILULLO
  • Patent number: 10970455
    Abstract: Methods and apparatus for creating an improved VLSI design. In-context timing analysis of a nominal VLSI design is performed and at least one assigned apportionment adjustment is determined for a sub-block of the nominal VLSI design. One or more slack adjustments are derived for at least one port of the sub-block based on the at least one apportionment adjustment and the one or more slack adjustments are applied to the in-context timing analysis to simulate a post optimization version of the sub-block. The in-context timing analysis is repeated using the one or more applied slack adjustments to generate the improved VLSI design.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: April 6, 2021
    Assignee: International Business Machines Corporation
    Inventors: Debjit Sinha, Adil Bhanji, Nathaniel Douglas Hieter
  • Patent number: 10831954
    Abstract: Efficiency of electronic design automation is increased by accessing a data structure characterizing a hierarchical integrated circuit design including sub-blocks each with a plurality of ports. For each given one of the ports of each of the sub-blocks, obtain a wire specification for a corresponding net connected to the given one of the ports in the design, and based on the wire specification, consult a technology-specific lookup table to determine at least one of a corresponding default driving cell and default electrical model for an external wire coupling one of the default driving cell and an actual driving cell to the given one of the ports. Optimize each of the sub-blocks out-of-context based on the at least one of default driving cells and default electrical models; verify in-context closure for the optimized sub-blocks; and, responsive to the in-context closure, update the data structure to reflect the optimized sub-blocks.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Debjit Sinha, Ravi Chander Ledalla, Chaobo Li, Adil Bhanji, Gregory Schaeffer, Michael Hemsley Wood
  • Publication number: 20190362043
    Abstract: A system and method involves partitioning a design of an integrated circuit into two or more hierarchical levels. A lowest level includes macros and a higher level includes some or all of the macros. Each of the macros includes two or more components. A macro timing model corresponding with each of the macros indicates a delay through the macro. The macro timing model corresponding with ones of the macros that are part of the higher level are loaded to perform higher-level timing analysis, which indicates a delay through the ones of the macros that are part of the higher level. Modified macro timing models corresponding with one or more of the macros are generated, and only the modified macro timing models associated with the macros that are part of the higher level modify corresponding loaded macro timing models to continue the higher-level timing analysis.
    Type: Application
    Filed: May 24, 2018
    Publication date: November 28, 2019
    Inventors: Hemlata Gupta, Alexander Suess, Adil Bhanji, Nathan Buck, Michel P. Robert, Edward Hughes, Kerim Kalafala, Jennifer E. Basile, Jack DiLullo, Adam Matheny, Michael H. Wood
  • Patent number: 10318683
    Abstract: A system and method to generate a clock domain-independent abstract of a component in an integrated circuit design. The method includes performing an initial analysis of the component using an initial clock value for each clock domain type, the clock domain types including a functional clock and a test clock, executing an abstractor to obtain a reduced order model of the initial analysis as a clock domain-dependent abstract, and obtaining original constraints associated with one or more circuit elements within the component from the clock domain-dependent abstract. Generating generalized constraints is based on clock domain-dependent constraints among the original constraints, and generating the clock domain-independent abstract is based on the generalized constraints. The method also includes obtaining a physical implementation based on one or more analyses using the clock domain-independent abstract.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Naiju K. Abdul, Adil Bhanji, Jack DiLullo, Kerim Kalafala, Jeremy J. Leitzen, Manish Verma
  • Publication number: 20190138916
    Abstract: Aspects include creating a knowledge base that identifies experts in a set of domains. Front-end processing is provided to an issue tracking system. The front-end processing includes receiving a report of an issue related to one of the domains, and accessing the knowledge base to locate an expert in the domain. The front-end processing also includes instructing the issue tracking system to route the received report of the issue to the located expert in the domain. The issue tracking system executes on a different processor than the front-end processing. Data collected from operation of the issue tracking system is monitored, and the knowledge base is updated based at least in part on the data collected from the operation of the issue tracking system.
    Type: Application
    Filed: November 9, 2017
    Publication date: May 9, 2019
    Inventors: Robert J. Allen, Adil Bhanji, Vasant B. Rao, Peter A. Twombly, Loma D. Vaishnav, Xin Zhao
  • Patent number: 10169503
    Abstract: A method, system and computer program product perform timing analysis of an integrated circuit design with callback-based constraint processing for clock domain independence. A timing graph representation of the integrated circuit design includes nodes interconnected by edges. Loading timing abstracts representing the nodes of the timing graph precedes obtaining a timing result based on propagating timing values and associated timing tags from an input to an output of the integrated circuit design and processing timing constraints at one or more of the nodes as callbacks. Each timing tag indicates a clock domain. After applying a design change, one or more modified timing tags that are added or changed as a result of the design change are determined. The timing constraints associated with the modified timing tags are processed as callbacks, and the timing result are re-computed.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Naiju K. Abdul, Adil Bhanji, Hemlata Gupta, Kerim Kalafala, Alex Rubin, Manish Verma
  • Publication number: 20180173833
    Abstract: A method, system and computer program product perform timing analysis of an integrated circuit design with callback-based constraint processing for clock domain independence. A timing graph representation of the integrated circuit design includes nodes interconnected by edges. Loading timing abstracts representing the nodes of the timing graph precedes obtaining a timing result based on propagating timing values and associated timing tags from an input to an output of the integrated circuit design and processing timing constraints at one or more of the nodes as callbacks. Each timing tag indicates a clock domain. After applying a design change, one or more modified timing tags that are added or changed as a result of the design change are determined. The timing constraints associated with the modified timing tags are processed as callbacks, and the timing result are re-computed.
    Type: Application
    Filed: February 15, 2018
    Publication date: June 21, 2018
    Inventors: Naiju K. Abdul, Adil Bhanji, Hemlata Gupta, Kerim Kalafala, Alex Rubin, Manish Verma
  • Patent number: 9977850
    Abstract: A method, system and computer program product perform timing analysis of an integrated circuit design with callback-based constraint processing for clock domain independence. A timing graph representation of the integrated circuit design includes nodes interconnected by edges. Loading timing abstracts representing the nodes of the timing graph precedes obtaining a timing result based on propagating timing values and associated timing tags from an input to an output of the integrated circuit design and processing timing constraints at one or more of the nodes as callbacks. Each timing tag indicates a clock domain. After applying a design change, one or more modified timing tags that are added or changed as a result of the design change are determined. The timing constraints associated with the modified timing tags are processed as callbacks, and the timing result are re-computed.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: May 22, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Naiju K. Abdul, Adil Bhanji, Hemlata Gupta, Kerim Kalafala, Alex Rubin, Manish Verma
  • Publication number: 20180018421
    Abstract: A method, system and computer program product perform timing analysis of an integrated circuit design with callback-based constraint processing for clock domain independence. A timing graph representation of the integrated circuit design includes nodes interconnected by edges. Loading timing abstracts representing the nodes of the timing graph precedes obtaining a timing result based on propagating timing values and associated timing tags from an input to an output of the integrated circuit design and processing timing constraints at one or more of the nodes as callbacks. Each timing tag indicates a clock domain. After applying a design change, one or more modified timing tags that are added or changed as a result of the design change are determined. The timing constraints associated with the modified timing tags are processed as callbacks, and the timing result are re-computed.
    Type: Application
    Filed: July 12, 2016
    Publication date: January 18, 2018
    Inventors: Naiju K. Abdul, Adil Bhanji, Hemlata Gupta, Kerim Kalafala, Alex Rubin, Manish Verma
  • Publication number: 20170337313
    Abstract: A system and method to generate a clock domain-independent abstract of a component in an integrated circuit design. The method includes performing an initial analysis of the component using an initial clock value for each clock domain type, the clock domain types including a functional clock and a test clock, executing an abstractor to obtain a reduced order model of the initial analysis as a clock domain-dependent abstract, and obtaining original constraints associated with one or more circuit elements within the component from the clock domain-dependent abstract. Generating generalized constraints is based on clock domain-dependent constraints among the original constraints, and generating the clock domain-independent abstract is based on the generalized constraints. The method also includes obtaining a physical implementation based on one or more analyses using the clock domain-independent abstract.
    Type: Application
    Filed: May 20, 2016
    Publication date: November 23, 2017
    Inventors: Naiju K. Abdul, Adil Bhanji, Jack DiLullo, Kerim Kalafala, Jeremy J. Leitzen, Manish Verma
  • Patent number: 9607124
    Abstract: The timing analysis of an integrated chip component using dynamic load sensitive timing feedback constraints maintaining the timing accuracy for all the boundary paths is achieved by capturing a reduced order representation for parasitic load within a component for each of its primary input and primary output along with sensitivities of the arrival time, the slew and the required arrival time to the load representation at the component parent level of hierarchy as part of generating load sensitive feedback constraints. During the out-of-context timing closure of the component, the base load representation and the sensitivities, and an updated load representation enables the calculation of the updated boundary constraint for an accurate timing analysis. The accuracy improvement increases a chip designer productivity during timing closure resulting in a shortened time to take the chip design through timing closure to manufacturing.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: March 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Adil Bhanji, Kerim Kalafala, Ravichander Ledalla, Debjit Sinha, Chandramouli Visweswariah, Michael H. Wood
  • Publication number: 20160314236
    Abstract: The timing analysis of an integrated chip component using dynamic load sensitive timing feedback constraints maintaining the timing accuracy for all the boundary paths is achieved by capturing a reduced order representation for parasitic load within a component for each of its primary input and primary output along with sensitivities of the arrival time, the slew and the required arrival time to the load representation at the component parent level of hierarchy as part of generating load sensitive feedback constraints. During the out-of-context timing closure of the component, the base load representation and the sensitivities, and an updated load representation enables the calculation of the updated boundary constraint for an accurate timing analysis. The accuracy improvement increases a chip designer productivity during timing closure resulting in a shortened time to take the chip design through timing closure to manufacturing.
    Type: Application
    Filed: April 21, 2015
    Publication date: October 27, 2016
    Inventors: Adil Bhanji, Kerim Kalafala, Ravichander Ledalla, Debjit Sinha, Chandramouli Visweswariah, Michael H. Wood
  • Patent number: 8185371
    Abstract: A modeling system includes a processor with software that performs static timing analysis (STA) on a design model. STA software executes a static timing analysis (STA) run with shortened clock cycles to model full cycle clock variability. Designers or other entities interpret the results of the shortened STA run data by performing modeling on the output data to generate slack data for design model data paths. STA software executes an STA run with an extended clock cycle to automatically separate half cycle data path (HCDP) slack data from full cycle data path (FCDP) slack data. The full and half cycle clock variability method may automatically adjust slack data for all half cycle data paths (HCDP)s to account for the additional half cycle variation (AHCV) and half cycle clock edge variability that may penalize the design model results in a real hardware implementation.
    Type: Grant
    Filed: April 15, 2009
    Date of Patent: May 22, 2012
    Assignee: International Business Machines Corporation
    Inventors: Adil Bhanji, Sean Michael Carey, Jack Dilullo, Prashant D Joshi, Don Richard Rozales, Vern Anthony Victoria, Albert Thomas Williams
  • Patent number: 8122404
    Abstract: A method for performing a hierarchical statistical timing analysis of an integrated circuit (IC) chip design by abstracting one or more macros of the design. The method includes performing a statistical static timing analysis of at least one macro; performing a statistical abstraction of the macro to obtain a statistical abstract model of the macro timing characteristics; applying the statistical abstract model as the timing model for each occurrence of the macro leading to a simplified IC chip design; and performing a hierarchical statistical timing analysis of the simplified chip design. The method achieves a context aware statistical abstraction, where a generated statistical abstract model is instantiated for each macro of the chip during statistical static timing analysis at the chip level, providing a compressed and pruned statistical timing abstraction and reducing the model-size during the statistical abstraction.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: February 21, 2012
    Assignee: International Business Machines Corporation
    Inventors: Debjit Sinha, Adil Bhanji, Barry L. Dorfman, Kerim Kalafala, Natesan Venkateswaran, Chandramouli Visweswariah
  • Patent number: 8103997
    Abstract: A method for converting interconnect parasitics of an interconnect network into slew dependent pin capacitances utilizes charge matching between predetermined voltage thresholds. During timing abstraction of a macro, parasitics of interconnects connected to the primary inputs are represented as slew dependent pin capacitances in an abstract model being created. Interconnect model order reduction is employed to speed the process. The generated abstract is subsequently used in place of each occurrence of the macro during chip level hierarchical static timing analysis, leading to an enhanced accuracy of the timing analysis of the logic components driving the abstracts.
    Type: Grant
    Filed: April 20, 2009
    Date of Patent: January 24, 2012
    Assignee: International Business Machines Corporation
    Inventors: Debjit Sinha, Soroush Abbaspour, Adil Bhanji, Jeffrey M. Ritzinger
  • Publication number: 20100269083
    Abstract: A method for converting interconnect parasitics of an interconnect network into slew dependent pin capacitances utilizes charge matching between predetermined voltage thresholds. During timing abstraction of a macro, parasitics of interconnects connected to the primary inputs are represented as slew dependent pin capacitances in an abstract model being created. Interconnect model order reduction is employed to speed the process. The generated abstract is subsequently used in place of each occurrence of the macro during chip level hierarchical static timing analysis, leading to an enhanced accuracy of the timing analysis of the logic components driving the abstracts.
    Type: Application
    Filed: April 20, 2009
    Publication date: October 21, 2010
    Applicant: International Business Machines Corporation
    Inventors: Debjit Sinha, Soroush Abbaspour, Adil Bhanji, Jeffrey M. Ritzinger
  • Publication number: 20100268522
    Abstract: A modeling system includes a processor with software that performs static timing analysis (STA) on a design model. STA software executes a static timing analysis (STA) run with shortened clock cycles to model full cycle clock variability. Designers or other entities interpret the results of the shortened STA run data by performing modeling on the output data to generate slack data for design model data paths. STA software executes an STA run with an extended clock cycle to automatically separate half cycle data path (HCDP) slack data from full cycle data path (FCDP) slack data. The full and half cycle clock variability method may automatically adjust slack data for all half cycle data paths (HCDP)s to account for the additional half cycle variation (AHCV) and half cycle clock edge variability that may penalize the design model results in a real hardware implementation.
    Type: Application
    Filed: April 15, 2009
    Publication date: October 21, 2010
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM Corporation
    Inventors: Adil Bhanji, Sean Michael Carey, Jack Dilullo, Prashant D Joshi, Don Richard Rozales, Vern Anthony Victoria, Albert Thomas Williams
  • Patent number: 7788617
    Abstract: An accurate method to compute the capacitance at a pin whose capacitance is slew dependant. The method uses existing library characterized data and provides an equation based approach which can easily be integrated in static timing analysis without the added resource needs that an iterative approach would require. An RC/RLC network from slew and output load dependent pin capacitance tables is generated. The resulting linear network which models the pin capacitance is then stitched to the original interconnect network and used to calculate the propagation delay across a gate and corresponding interconnect.
    Type: Grant
    Filed: March 6, 2008
    Date of Patent: August 31, 2010
    Assignee: International Business Machines Corporation
    Inventors: Adil Bhanji, Soroush Abbaspour, Peter Feldmann, Debjit Sinha
  • Publication number: 20100211922
    Abstract: A method for performing a hierarchical statistical timing analysis of an integrated circuit (IC) chip design by abstracting one or more macros of the design. The method includes performing a statistical static timing analysis of at least one macro; performing a statistical abstraction of the macro to obtain a statistical abstract model of the macro timing characteristics; applying the statistical abstract model as the timing model for each occurrence of the macro leading to a simplified IC chip design; and performing a hierarchical statistical timing analysis of the simplified chip design. The method achieves a context aware statistical abstraction, where a generated statistical abstract model is instantiated for each macro of the chip during statistical static timing analysis at the chip level, providing a compressed and pruned statistical timing abstraction and reducing the model-size during the statistical abstraction.
    Type: Application
    Filed: February 19, 2009
    Publication date: August 19, 2010
    Applicant: International Business Machines Corporation
    Inventors: Debjit Sinha, Adil Bhanji, Barry L. Dorfman, Kerim Kalafala, Natesan Venkateswaran, Chandramouli Visweswariah