Abstract: A time-resolved multi-gate ion sensitive field effect transducer, including a silicon layer, a P-doped region in the silicon layer and a first electrode in electric connection with the P doped region, a N-doped region in the silicon layer and a second electrode in electric connection with the N-doped region, a general channel area defined in the silicon layer between the P-doped and N-doped regions, a first gate structure forming a sensing area, the first gate structure including a first insulating layer on the silicon layer, the sensing area configured to receive an electrolyte solution, and a third electrode at the sensing area configured to be in contact with the electrolyte solution, the first gate structure configured to generate a first channel area in the silicon layer for providing a first potential barrier, and a second gate structure configured to generate a second channel area in the silicon layer for providing a second potential barrier.

Abstract: A method of operating a phase lock loop includes generating a control voltage based on both an output signal of a voltage-controlled oscillator and a reference signal. An operating mode is selected from one of a high-gain mode, a zero-gain mode and a low-gain mode based on the control voltage. The phase lock loop is operated in the selected one of the high-gain mode, the zero-gain mode, and the low-gain mode. The control voltage is offset to generate an offset voltage based on the selected operating mode. The output signal is generated based on the offset voltage.

Abstract: An apparatus includes a phase locked loop (PLL). The phase locked loop (PLL) has coarse tuning (CT), fine tuning-integer (FT-i), fine tuning fractional (FT-f), frequency modulator tuning-fractional (FMT-f), and narrowband (NB) modes of operation.

Abstract: A method of operating a phase lock loop includes generating a control voltage based on both an output signal of a voltage-controlled oscillator and a reference signal. An operating mode is selected from one of a high-gain mode, a zero-gain mode and a low-gain mode based on the control voltage. The phase lock loop is operated in the selected one of the high-gain mode, the zero-gain mode, and the low-gain mode. The control voltage is offset to generate an offset voltage based on the selected operating mode. The output signal is generated based on the offset voltage.

Abstract: A phase lock loop (PLL) frequency synthesizer includes a reconfigurable voltage controlled oscillator (VCO) with three modes of operation: a Linear-High-gain, Zero-gain, and Low-gain mode. During the linear high gain mode, the VCO enables an analogue self-calibration of the PLL over a wide frequency tuning range. Control voltage at the input of the VCO is varied by the PLL to provide an output frequency. When the PLL is locked, the VCO is switched to the Zero-gain mode while maintaining the output.

Abstract: A method and apparatus for a fast and automatic setting of the phase locked loop (PLL) output frequency that significantly improves linearity, locking range as well as spectrum purity, jitter and phase noise performances is disclosed. In one embodiment, a PLL frequency synthesizer is disclosed having a reconfigurable voltage controlled oscillator VCO with three modes of operation: a Linear-High-gain, Zero-gain, and Low-gain mode. During a first tuning operation, the VCO work in a linear high gain mode, enabling a totally analogue self-calibration of the PLL over a wide frequency tuning range and with a fast settling time. During this operation the control voltage at the input of the VCO is varied by the PLL until the appropriate output frequency is found. A method for providing a linear variation of the frequency over all the voltage tuning range during this mode is disclosed. When the loop is locked, the VCO is automatically switched to the Zero-gain mode while keeping its frequency unchanged.