Patents by Inventor Adil M. Sadik

Adil M. Sadik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Cache memory with transient storage for cache lines
    Patent number: 11023162
    Abstract: Techniques are disclosed relating to caches that support transient storage fields for cache entries. In some embodiments, cache circuitry includes a set of multiple cache entries that each include a tag field and a data field. In some embodiments, transient storage circuitry includes a transient storage field for each of the multiple cache entries. In some embodiments, cache control circuitry stores received first data in the data field of a cache entry and stores received transient data in a corresponding transient storage field. In response to an eviction determination for the cache entry, however, the cache control circuitry may write the first data but not the transient data to a backing memory for the cache circuitry. In various embodiments, disclosed techniques may allow caching additional data that is transient without increasing bandwidth to the backing memory.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: June 1, 2021
    Assignee: Apple Inc.
    Inventors: Jeffrey T. Brady, Sindhuja Sethuraman, Frank W. Liljeros, Adil M. Sadik
  • Cache Memory with Transient Storage for Cache Lines
    Publication number: 20210055883
    Abstract: Techniques are disclosed relating to caches that support transient storage fields for cache entries. In some embodiments, cache circuitry includes a set of multiple cache entries that each include a tag field and a data field. In some embodiments, transient storage circuitry includes a transient storage field for each of the multiple cache entries. In some embodiments, cache control circuitry stores received first data in the data field of a cache entry and stores received transient data in a corresponding transient storage field. In response to an eviction determination for the cache entry, however, the cache control circuitry may write the first data but not the transient data to a backing memory for the cache circuitry. In various embodiments, disclosed techniques may allow caching additional data that is transient without increasing bandwidth to the backing memory.
    Type: Application
    Filed: August 22, 2019
    Publication date: February 25, 2021
    Inventors: Jeffrey T. Brady, Sindhuja Sethuraman, Frank W. Liljeros, Adil M. Sadik