Patents by Inventor Adir Zevulun

Adir Zevulun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12131132
    Abstract: An Integrated Montgomery Calculation Engine (IMCE), for multiplying two multiplicands modulo a predefined number, includes a Carry Save Adder (CSA) circuit and control circuitry. The CSA circuit has multiple inputs, and has outputs including a sum output and a carry output. The control circuitry is coupled to the inputs and the outputs of the CSA circuit and is configured to operate the CSA circuit in at least (i) a first setting that calculates a Montgomery precompute value and (ii) a second setting that calculates a Montgomery multiplication of the two multiplicands.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: October 29, 2024
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Adir Zevulun, Uria Basher, Nir Shmuel, Ben Witulski
  • Patent number: 12079594
    Abstract: A Montgomery multiplication apparatus (MMA), for multiplying two multiplicands modulo a predefined number, includes a pre-compute circuit and a Montgomery multiplication circuit. The pre-compute circuit is configured to compute a Montgomery pre-compute value by performing a series of iterations. In a given iteration, the pre-compute circuit is configured to modify one or more intermediate values by performing bit-wise operations on the intermediate values calculated in a preceding iteration. The Montgomery multiplication circuit is configured to multiply the two multiplicands, modulo the predefined number, by performing a plurality of Montgomery reduction operations using the Montgomery pre-compute value computed by the pre-compute circuit.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: September 3, 2024
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Adir Zevulun, Uria Basher, Nir Shmuel, Ben Witulski
  • Publication number: 20220269487
    Abstract: An Integrated Montgomery Calculation Engine (IMCE), for multiplying two multiplicands modulo a predefined number, includes a Carry Save Adder (CSA) circuit and control circuitry. The CSA circuit has multiple inputs, and has outputs including a sum output and a carry output. The control circuitry is coupled to the inputs and the outputs of the CSA circuit and is configured to operate the CSA circuit in at least (i) a first setting that calculates a Montgomery precompute value and (ii) a second setting that calculates a Montgomery multiplication of the two multiplicands.
    Type: Application
    Filed: February 22, 2021
    Publication date: August 25, 2022
    Inventors: Adir Zevulun, Uria Basher, Nir Shmuel, Ben Witulski
  • Publication number: 20220269488
    Abstract: A Montgomery multiplication apparatus (MMA), for multiplying two multiplicands modulo a predefined number, includes a pre-compute circuit and a Montgomery multiplication circuit. The pre-compute circuit is configured to compute a Montgomery pre-compute value by performing a series of iterations. In a given iteration, the pre-compute circuit is configured to modify one or more intermediate values by performing bit-wise operations on the intermediate values calculated in a preceding iteration. The Montgomery multiplication circuit is configured to multiply the two multiplicands, modulo the predefined number, by performing a plurality of Montgomery reduction operations using the Montgomery pre-compute value computed by the pre-compute circuit.
    Type: Application
    Filed: February 22, 2021
    Publication date: August 25, 2022
    Inventors: Adir Zevulun, Uria Basher, Nir Shmuel, Ben Witulski
  • Patent number: 10171103
    Abstract: A hardware compression architecture including a shift register including: a plurality of sequentially coupled stages and a window stage coupled at an output end of the shift register, the shift register configured to receive an uncompressed data stream at an input end and output the uncompressed data from the window stage; a plurality of comparators each coupled to receive a data value held in a corresponding stage of the shift register and a data value held in the window stage, each of the comparators being configured to output a comparison result indicating whether the received stage value and the window stage data value match; logic, coupled to the comparators to receive the comparison results, to selectively compute one or more indexes based on the comparisons; and an encoder coupled to receive the one or more indexes and output, based on the one or more indexes, a position of a matching data value and a length of a matching sequence of data values.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: January 1, 2019
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Adir Zevulun, Noam Rom, Nir Shmuel