Abstract: Technology for compact data latches. Two global driver transistors are each connected to a large number of compact data latches. The global driver transistors may be operated during a simultaneous latch operation in each of the compact data latches. A latch operation may discharge a high voltage from a latch output, depending on whether that output is to go from the high voltage to a low voltage. Such discharge could lead to a shoot through voltage and/or fight between a PMOS and an NMOS transistor in the data latch. Turning off one of the global driver transistors during a latch operation prevents shoot through current and also prevents a fight between a PMOS and an NMOS transistor in the data latch. The global driver transistors occupy a small chip area.

Abstract: Technology for compact data latches. Two global driver transistors are each connected to a large number of compact data latches. The global driver transistors may be operated during a simultaneous latch operation in each of the compact data latches. A latch operation may discharge a high voltage from a latch output, depending on whether that output is to go from the high voltage to a low voltage. Such discharge could lead to a shoot through voltage and/or fight between a PMOS and an NMOS transistor in the data latch. Turning off one of the global driver transistors during a latch operation prevents shoot through current and also prevents a fight between a PMOS and an NMOS transistor in the data latch. The global driver transistors occupy a small chip area.