Patents by Inventor Adithya Bhaskaran

Adithya Bhaskaran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Low power and robust level-shifting pulse latch for dual-power memories
    Patent number: 11972834
    Abstract: A level-shifting pulse latch is provided for a self-timed memory clock signal for a memory. The level-shifting pulse latch includes a system-power-domain-to-memory-power-domain level-shifter that inverts and level-shifts a system clock signal into an inverted version of the system clock signal. A pass transistor controls whether the inverted version of the system clock signal drives a memory-power-domain latch to produce the self-timed memory clock signal.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: April 30, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Adithya Bhaskaran, Rahul Sahu, Sharad Kumar Gupta
  • Low Power and Robust Level-Shifting Pulse Latch for Dual-Power Memories
    Publication number: 20220293148
    Abstract: A level-shifting pulse latch is provided for a self-timed memory clock signal for a memory. The level-shifting pulse latch includes a system-power-domain-to-memory-power-domain level-shifter that inverts and level-shifts a system clock signal into an inverted version of the system clock signal. A pass transistor controls whether the inverted version of the system clock signal drives a memory-power-domain latch to produce the self-timed memory clock signal.
    Type: Application
    Filed: November 9, 2020
    Publication date: September 15, 2022
    Inventors: Adithya Bhaskaran, Rahul Sahu, Sharad Kumar Gupta
  • Memory with high-speed and area-efficient read path
    Patent number: 11315609
    Abstract: A read path for a memory is provided that includes an integrated sense mixing and redundancy shift stage coupled between a sense amplifier and a data latch. The data latch is integrated with a level shifter.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: April 26, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Adithya Bhaskaran, Mukund Narasimhan, Shiba Narayan Mohanty
  • Low-power and high-density core-power lowering for memory write assist
    Patent number: 11074967
    Abstract: A memory is provided that includes a current mirror that controls the amount of current conducted by a head-switch transistor for a memory power supply rail during a core-power-lowering write assist period.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: July 27, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Adithya Bhaskaran, Mukund Narasimhan, Shiba Narayan Mohanty
  • LOW-POWER AND HIGH-DENSITY CORE-POWER LOWERING FOR MEMORY WRITE ASSIST
    Publication number: 20210020234
    Abstract: A memory is provided that includes a current mirror that controls the amount of current conducted by a head-switch transistor for a memory power supply rail during a core-power-lowering write assist period.
    Type: Application
    Filed: September 30, 2020
    Publication date: January 21, 2021
    Inventors: Adithya BHASKARAN, Mukund NARASIMHAN, Shiba Narayan MOHANTY
  • MEMORY WITH HIGH-SPEED AND AREA-EFFICIENT READ PATH
    Publication number: 20210020206
    Abstract: A read path for a memory is provided that includes an integrated sense mixing and redundancy shift stage coupled between a sense amplifier and a data latch. The data latch is integrated with a level shifter.
    Type: Application
    Filed: September 30, 2020
    Publication date: January 21, 2021
    Inventors: Adithya BHASKARAN, Mukund NARASIMHAN, Shiba Narayan MOHANTY
  • Memory with high-speed and area-efficient read path
    Patent number: 10854246
    Abstract: A read path for a memory is provided that includes an integrated sense mixing and redundancy shift stage coupled between a sense amplifier and a data latch. The data latch is integrated with a level shifter.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: December 1, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Adithya Bhaskaran, Mukund Narasimhan, Shiba Narayan Mohanty
  • Memory with High-Speed and Area-Efficient Read Path
    Publication number: 20200372939
    Abstract: A read path for a memory is provided that includes an integrated sense mixing and redundancy shift stage coupled between a sense amplifier and a data latch. The data latch is integrated with a level shifter.
    Type: Application
    Filed: May 23, 2019
    Publication date: November 26, 2020
    Inventors: Adithya Bhaskaran, Mukund Narasimhan, Shiba Narayan Mohanty
  • Low-power and high-density core-power lowering for memory write assist
    Patent number: 10832764
    Abstract: A memory is provided that includes a current mirror that controls the amount of current conducted by a head-switch transistor for a memory power supply rail during a core-power-lowering write assist period.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: November 10, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Adithya Bhaskaran, Mukund Narasimhan, Shiba Narayan Mohanty
  • SRAM write yield enhancement with pull-up strength modulation
    Patent number: 10811086
    Abstract: A memory is provided that includes a negative bit line boost circuit for boosting a discharged bit line to a negative voltage during a negative bit line boost period for a write operation to a selected column in the memory. The memory also includes a core voltage control circuit configured to float a core power supply voltage for the selected column during the negative bit line boost period.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: October 20, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Shiba Narayan Mohanty, Sharad Kumar Gupta, Rahul Sahu, Pradeep Raj, Veerabhadra Rao Boda, Adithya Bhaskaran, Akshdeepika
  • LOW-POWER AND HIGH-DENSITY CORE-POWER LOWERING FOR MEMORY WRITE ASSIST
    Publication number: 20200251163
    Abstract: A memory is provided that includes a current mirror that controls the amount of current conducted by a head-switch transistor for a memory power supply rail during a core-power-lowering write assist period.
    Type: Application
    Filed: February 6, 2019
    Publication date: August 6, 2020
    Inventors: Adithya Bhaskaran, Mukund Narasimhan, Shiba Narayan Mohanty
  • Flexible power sequencing for dual-power memory
    Patent number: 10446196
    Abstract: A dual-power-domain SRAM is disclosed in which the dual power domains may be powered up or down in whatever order is desired. For example, a (CX) power domain may be powered up first, followed by a memory (MX) power domain. Conversely, the MX power domain may be powered up prior to the CX domain.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: October 15, 2019
    Assignee: Qualcomm Incorporated
    Inventors: Mukund Narasimhan, Sharad Kumar Gupta, Adithya Bhaskaran, Sei Seung Yoon