Patents by Inventor Adithya Hrudhayan KRISHNAMURTHY

Adithya Hrudhayan KRISHNAMURTHY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240103951
    Abstract: A receiver device includes detection logic, error counter logic, and threshold logic. The detection detects frame errors in data frames received by a transmitter device. The error counter logic increments a first value of an error count responsive to each error signal, indicative of a frame error in a data frame, received from the detection logic. The error counter logic reduces the first value to a second value (non-zero value) for the error count responsive to receiving a decrement signal and a period marker signal corresponding to a programmable period. The error counter logic resets the first value or the second value of the error count to zero responsive to receiving a reset signal. The threshold logic compares a current value of the error count with a threshold number of frame errors and output an interrupt responsive to the current value satisfying the threshold number of frame errors.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 28, 2024
    Inventors: Adithya Hrudhayan Krishnamurthy, Ish Chadha
  • Patent number: 11880265
    Abstract: A receiver device includes detection logic, an error counter, and an interrupt logic. The detection logic is to receive a first set of data frames and detect one or more frame errors in the first set of data frames. The error counter is to store a number of the one or more frame errors detected in the first set of data frames. The interrupt logic can be coupled to the error counter. The interrupt logic is to specify a period and compare the number of the one or more frame errors with a threshold number of frame errors during the period, where the interrupt logic is to indicate an interrupt responsive to the number of the one or more frame errors detected within the period satisfying the threshold number of frame errors.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: January 23, 2024
    Assignee: NVIDIA Corporation
    Inventors: Adithya Hrudhayan Krishnamurthy, Ish Chadha
  • Publication number: 20230209405
    Abstract: A system includes a link having one or more data paths and a device coupled with the link and including a data link (DL) transmitter and a buffer. The device is to write one or more bits corresponding to a operation to a first portion of a data frame in response to an indication, the data frame comprising a second portion comprising data. The device is to transmit the first portion and the second portion of the data frame via the one or more data paths in response to writing the one or more bits corresponding to the operation. The device is to store the data frame at the buffer in response to writing the one or more bits corresponding to the operation.
    Type: Application
    Filed: October 18, 2022
    Publication date: June 29, 2023
    Inventors: Adithya Hrudhayan Krishnamurthy, Ish Chadha
  • Publication number: 20230195551
    Abstract: A receiver device includes detection logic, an error counter, and an interrupt logic. The detection logic is to receive a first set of data frames and detect one or more frame errors in the first set of data frames. The error counter is to store a number of the one or more frame errors detected in the first set of data frames. The interrupt logic can be coupled to the error counter. The interrupt logic is to specify a period and compare the number of the one or more frame errors with a threshold number of frame errors during the period, where the interrupt logic is to indicate an interrupt responsive to the number of the one or more frame errors detected within the period satisfying the threshold number of frame errors.
    Type: Application
    Filed: December 21, 2021
    Publication date: June 22, 2023
    Inventors: Adithya Hrudhayan Krishnamurthy, Ish Chadha
  • Publication number: 20230050617
    Abstract: A system includes a first device and a second device coupled to a link. The first device is to transmit one or more request frames for synchronization of a data layer, each request frame including a quantity of bits and an error code. The second device is to receive a first set of bits corresponding to the quantity of bits in each request frame. The second device is to perform an error decode operation on the first set of bits using a first portion of the first set of bits and determine the first set of bits correspond to a frame boundary of the one more request frames responsive to a success of the error decode operation. The second device is to transmit an acknowledgement of the synchronization of the data layer based on determining the first set of bits corresponds to the frame boundary.
    Type: Application
    Filed: August 13, 2021
    Publication date: February 16, 2023
    Inventors: Adithya Hrudhayan Krishnamurthy, Ish Chadha
  • Patent number: 11569939
    Abstract: A system includes a first device and a second device coupled to a link. The first device is to transmit one or more request frames for synchronization of a data layer, each request frame including a quantity of bits and an error code. The second device is to receive a first set of bits corresponding to the quantity of bits in each request frame. The second device is to perform an error decode operation on the first set of bits using a first portion of the first set of bits and determine the first set of bits correspond to a frame boundary of the one more request frames responsive to a success of the error decode operation. The second device is to transmit an acknowledgement of the synchronization of the data layer based on determining the first set of bits corresponds to the frame boundary.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: January 31, 2023
    Assignee: NVIDIA Corporation
    Inventors: Adithya Hrudhayan Krishnamurthy, Ish Chadha
  • Patent number: 11010954
    Abstract: A computer-implemented redundant-coverage discard method and apparatus for reducing pixel shader work in a tile-based graphics rendering pipeline is disclosed. A coverage block information (CBI) FIFO buffer is disposed within an early coverage discard (ECD) logic section. The FIFO buffer receives and buffers coverage blocks in FIFO order. At least one coverage block that matches the block position within the TCPM is updated. The TCPM stores per-pixel primitive coverage information. The FIFO buffer buffers a moving window of the coverage blocks. Incoming primitive information associated with the coverage blocks is compared with the per-pixel primitive coverage information stored in the tile coverage-primitive map (TCPM) table at the corresponding positions for the live coverages only. Any preceding overlapping coverage within the moving window of the coverage blocks is rejected. An alternate embodiment uses a doubly linked-list rather than a FIFO buffer.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: May 18, 2021
    Inventors: Nilanjan Goswami, Derek Lentz, Adithya Hrudhayan Krishnamurthy, David C. Tannenbaum
  • Publication number: 20200184715
    Abstract: A computer-implemented redundant-coverage discard method and apparatus for reducing pixel shader work in a tile-based graphics rendering pipeline is disclosed. A coverage block information (CBI) FIFO buffer is disposed within an early coverage discard (ECD) logic section. The FIFO buffer receives and buffers coverage blocks in FIFO order. At least one coverage block that matches the block position within the TCPM is updated. The TCPM stores per-pixel primitive coverage information. The FIFO buffer buffers a moving window of the coverage blocks. Incoming primitive information associated with the coverage blocks is compared with the per-pixel primitive coverage information stored in the tile coverage-primitive map (TCPM) table at the corresponding positions for the live coverages only. Any preceding overlapping coverage within the moving window of the coverage blocks is rejected. An alternate embodiment uses a doubly linked-list rather than a FIFO buffer.
    Type: Application
    Filed: June 11, 2019
    Publication date: June 11, 2020
    Inventors: Nilanjan GOSWAMI, Derek LENTZ, Adithya Hrudhayan KRISHNAMURTHY, David C. TANNENBAUM