Abstract: Approaches for configuring a system-on-chip (SOC) include generating component images for components of the SOC. A first component image is for a platform management controller, a second component image is for programmable logic, and a third component image is for a processor subsystem. The plurality of component images are assembled into a programmable device image, and the programmable device image is input to the platform management controller. The platform management controller is booted from the first component image, the programmable logic is configured with the second component image by the platform management controller in executing the first component image, and the processor subsystem is configured with the third component image by the platform management controller in executing the first component image.

Abstract: Some examples described herein relate to global mapping of program nodes of a netlist of an application. In an example, a design system includes a processor and a memory coupled to the processor. The memory stores instruction code. The processor is configured to execute the instruction code to obtain a netlist of an application. The netlist contains program nodes and respective edges between the program nodes. The application is to be implemented on a device comprising an array of data processing engines. The processor is also configured to execute the instruction code to generate a global mapping of the program nodes based on a representation of the array of data processing engines and using an integer linear programming (ILP) algorithm; generate a detailed mapping of the program nodes based on the global mapping; and translate the detailed mapping to a file.

Abstract: When a first sub-circuit of a programmable integrated circuit (“IC”) is to be deactivated, a global write enable (GWE) signal is deasserted. In response to deassertion of the GWE signal and a first memory cell associated with the first sub-circuit being in a first state, flip-flops in the first sub-circuit are disabled from changing state. In response to memory cells associated with sub-circuits other than the first sub-circuit being in a second state, flip-flops in the other sub-circuits are enabled to change state. When the first sub-circuit is to be activated, the GWE signal is asserted. Logic implemented by the first sub-circuit is preserved between the deasserting and the asserting of the GWE signal. In response to assertion of the GWE signal and the first memory cell associated with the first sub-circuit being in the first state, flip-flops in the first sub-circuit are enabled to change state.